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drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV
This allows us to get the right vblank interrupt frequency. v2: pull in register definition Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -556,6 +556,8 @@
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#define IIR 0x020a4
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#define IMR 0x020a8
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#define ISR 0x020ac
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#define VLV_GUNIT_CLOCK_GATE 0x182060
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#define GCFG_DIS (1<<8)
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#define VLV_IIR_RW 0x182084
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#define VLV_IER 0x1820a0
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#define VLV_IIR 0x1820a4
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@ -3755,6 +3755,13 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
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SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
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PLANEA_FLIPDONE_INT_EN);
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/*
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* WaDisableVLVClockGating_VBIIssue
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* Disable clock gating on th GCFG unit to prevent a delay
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* in the reporting of vblank events.
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*/
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I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
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}
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static void g4x_init_clock_gating(struct drm_device *dev)
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