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drm/tegra: Fixes for v4.15-rc1
This includes an update to the SOR pad clock programming needed because of some changes that went in through the clock tree. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAloVbGQTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoUzwD/4np5tShnMB4pp3TNpbbZ0x2wrbRc/f J3/ueUzWxGY1g2aFgRnQ91RRBo0BgjEFKQfLe1lxT4Q/7O81twtzluz7PDI3qHSS sAvNrJLAudcWIGAsIs6A8GUlDIwvenuscw5QoLPimpdwFopKl89Smrzubn3ZXzok VOG+6KcUY9sUMINl/EvBDJCm6K4Hb6wMrOohwOug0qkL126Oz0j1kHCbQz28jDwL DiDR9RBx+c0DHWfkpiE9IJ9I266QHDtKSmMi43+Bu/gX74HW/ipN+eZQbzIcFyIT OM6s4pPUZtNI4e4N+zQ8Uj3JwccjsQtQo+mwFw0TzzdfXkqxC7feOENEzmOdwFWW X99ESrOPdbnvGLorGu3LtubsshXkvU3ME6wt+dNDIJjlg/+b1QwPKN8rVTTcw+ey xrcqiqeoPMSDhxTOZtAuskg3kDO1RcnnftUInkqyZ1bj0BcIdXW+e7Oz5w1Zasp7 ozleNL+XqrKTNKDeq6iJrPvFbyUR5TuGF9GmcIJegzTDf+FLDHhc1cEzPVmmDD5B vSdO+V5gpVefep8HEu/xS4L/oMr9tr6xVrQ8zNtbuWyt0uA27YRIsaagJ5ebsJCg W3AgftB35mZm1mJ8b4zv9q3UWAc2EvFxFGrzk1SIzxFQbmaDjuB3ZGgBjcg0lhD7 hBGbv9jqL9IuLQ== =JFFp -----END PGP SIGNATURE----- Merge tag 'drm/tegra/for-4.15-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Fixes for v4.15-rc1 This includes an update to the SOR pad clock programming needed because of some changes that went in through the clock tree. * tag 'drm/tegra/for-4.15-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: sor: Reimplement pad clock
This commit is contained in:
Dave Airlie
commit
2d56131006
@ -174,9 +174,9 @@ struct tegra_sor {
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struct reset_control *rst;
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struct clk *clk_parent;
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struct clk *clk_brick;
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struct clk *clk_safe;
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struct clk *clk_src;
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struct clk *clk_out;
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struct clk *clk_pad;
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struct clk *clk_dp;
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struct clk *clk;
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@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
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clk_disable_unprepare(sor->clk);
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err = clk_set_parent(sor->clk, parent);
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err = clk_set_parent(sor->clk_out, parent);
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if (err < 0)
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return err;
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@ -266,24 +266,24 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
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return 0;
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}
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struct tegra_clk_sor_brick {
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struct tegra_clk_sor_pad {
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struct clk_hw hw;
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struct tegra_sor *sor;
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};
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static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw)
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static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
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{
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return container_of(hw, struct tegra_clk_sor_brick, hw);
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return container_of(hw, struct tegra_clk_sor_pad, hw);
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}
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static const char * const tegra_clk_sor_brick_parents[] = {
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static const char * const tegra_clk_sor_pad_parents[] = {
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"pll_d2_out0", "pll_dp"
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};
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static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
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static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
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{
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struct tegra_clk_sor_brick *brick = to_brick(hw);
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struct tegra_sor *sor = brick->sor;
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struct tegra_clk_sor_pad *pad = to_pad(hw);
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struct tegra_sor *sor = pad->sor;
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u32 value;
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value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
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@ -304,10 +304,10 @@ static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index)
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return 0;
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}
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static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
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static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
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{
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struct tegra_clk_sor_brick *brick = to_brick(hw);
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struct tegra_sor *sor = brick->sor;
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struct tegra_clk_sor_pad *pad = to_pad(hw);
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struct tegra_sor *sor = pad->sor;
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u8 parent = U8_MAX;
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u32 value;
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@ -328,33 +328,33 @@ static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw)
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return parent;
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}
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static const struct clk_ops tegra_clk_sor_brick_ops = {
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.set_parent = tegra_clk_sor_brick_set_parent,
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.get_parent = tegra_clk_sor_brick_get_parent,
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static const struct clk_ops tegra_clk_sor_pad_ops = {
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.set_parent = tegra_clk_sor_pad_set_parent,
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.get_parent = tegra_clk_sor_pad_get_parent,
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};
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static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor,
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const char *name)
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static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
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const char *name)
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{
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struct tegra_clk_sor_brick *brick;
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struct tegra_clk_sor_pad *pad;
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struct clk_init_data init;
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struct clk *clk;
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brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL);
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if (!brick)
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pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
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if (!pad)
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return ERR_PTR(-ENOMEM);
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brick->sor = sor;
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pad->sor = sor;
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init.name = name;
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init.flags = 0;
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init.parent_names = tegra_clk_sor_brick_parents;
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init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents);
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init.ops = &tegra_clk_sor_brick_ops;
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init.parent_names = tegra_clk_sor_pad_parents;
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init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
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init.ops = &tegra_clk_sor_pad_ops;
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brick->hw.init = &init;
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pad->hw.init = &init;
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clk = devm_clk_register(sor->dev, &brick->hw);
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clk = devm_clk_register(sor->dev, &pad->hw);
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return clk;
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}
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@ -998,8 +998,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
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/* switch to safe parent clock */
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err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
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if (err < 0)
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if (err < 0) {
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dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
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return err;
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}
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value = tegra_sor_readl(sor, SOR_DP_PADCTL0);
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value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
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@ -2007,8 +2009,10 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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/* switch to safe parent clock */
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err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
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if (err < 0)
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if (err < 0) {
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dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
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return;
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}
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div = clk_get_rate(sor->clk) / 1000000 * 4;
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@ -2111,13 +2115,17 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
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tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
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/* switch to parent clock */
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err = clk_set_parent(sor->clk_src, sor->clk_parent);
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if (err < 0)
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dev_err(sor->dev, "failed to set source clock: %d\n", err);
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err = tegra_sor_set_parent_clock(sor, sor->clk_src);
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if (err < 0)
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err = clk_set_parent(sor->clk, sor->clk_parent);
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if (err < 0) {
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dev_err(sor->dev, "failed to set parent clock: %d\n", err);
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return;
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}
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err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
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if (err < 0) {
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dev_err(sor->dev, "failed to set pad clock: %d\n", err);
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return;
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}
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value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
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@ -2628,11 +2636,24 @@ static int tegra_sor_probe(struct platform_device *pdev)
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}
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if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
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sor->clk_src = devm_clk_get(&pdev->dev, "source");
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if (IS_ERR(sor->clk_src)) {
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err = PTR_ERR(sor->clk_src);
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dev_err(sor->dev, "failed to get source clock: %d\n",
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err);
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struct device_node *np = pdev->dev.of_node;
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const char *name;
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/*
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* For backwards compatibility with Tegra210 device trees,
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* fall back to the old clock name "source" if the new "out"
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* clock is not available.
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*/
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if (of_property_match_string(np, "clock-names", "out") < 0)
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name = "source";
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else
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name = "out";
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sor->clk_out = devm_clk_get(&pdev->dev, name);
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if (IS_ERR(sor->clk_out)) {
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err = PTR_ERR(sor->clk_out);
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dev_err(sor->dev, "failed to get %s clock: %d\n",
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name, err);
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goto remove;
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}
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}
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@ -2658,16 +2679,60 @@ static int tegra_sor_probe(struct platform_device *pdev)
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goto remove;
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}
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/*
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* Starting with Tegra186, the BPMP provides an implementation for
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* the pad output clock, so we have to look it up from device tree.
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*/
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sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
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if (IS_ERR(sor->clk_pad)) {
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if (sor->clk_pad != ERR_PTR(-ENOENT)) {
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err = PTR_ERR(sor->clk_pad);
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goto remove;
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}
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/*
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* If the pad output clock is not available, then we assume
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* we're on Tegra210 or earlier and have to provide our own
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* implementation.
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*/
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sor->clk_pad = NULL;
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}
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/*
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* The bootloader may have set up the SOR such that it's module clock
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* is sourced by one of the display PLLs. However, that doesn't work
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* without properly having set up other bits of the SOR.
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*/
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err = clk_set_parent(sor->clk_out, sor->clk_safe);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
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goto remove;
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}
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platform_set_drvdata(pdev, sor);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick");
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pm_runtime_put(&pdev->dev);
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/*
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* On Tegra210 and earlier, provide our own implementation for the
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* pad output clock.
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*/
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if (!sor->clk_pad) {
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err = pm_runtime_get_sync(&pdev->dev);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
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err);
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goto remove;
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}
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if (IS_ERR(sor->clk_brick)) {
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err = PTR_ERR(sor->clk_brick);
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dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err);
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sor->clk_pad = tegra_clk_sor_pad_register(sor,
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"sor1_pad_clkout");
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pm_runtime_put(&pdev->dev);
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}
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if (IS_ERR(sor->clk_pad)) {
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err = PTR_ERR(sor->clk_pad);
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dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
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err);
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goto remove;
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}
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