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drm/i915: Revoke mmaps and prevent access to fence registers across reset
Previously, we were able to rely on the recursive properties of
struct_mutex to allow us to serialise revoking mmaps and reacquiring the
FENCE registers with them being clobbered over a global device reset.
I then proceeded to throw out the baby with the bath water in order to
pursue a struct_mutex-less reset.
Perusing LWN for alternative strategies, the dilemma on how to serialise
access to a global resource on one side was answered by
https://lwn.net/Articles/202847/ -- Sleepable RCU:
1 int readside(void) {
2 int idx;
3 rcu_read_lock();
4 if (nomoresrcu) {
5 rcu_read_unlock();
6 return -EINVAL;
7 }
8 idx = srcu_read_lock(&ss);
9 rcu_read_unlock();
10 /* SRCU read-side critical section. */
11 srcu_read_unlock(&ss, idx);
12 return 0;
13 }
14
15 void cleanup(void)
16 {
17 nomoresrcu = 1;
18 synchronize_rcu();
19 synchronize_srcu(&ss);
20 cleanup_srcu_struct(&ss);
21 }
No more worrying about stop_machine, just an uber-complex mutex,
optimised for reads, with the overhead pushed to the rare reset path.
However, we do run the risk of a deadlock as we allocate underneath the
SRCU read lock, and the allocation may require a GPU reset, causing a
dependency cycle via the in-flight requests. We resolve that by declaring
the driver wedged and cancelling all in-flight rendering.
v2: Use expedited rcu barriers to match our earlier timing
characteristics.
v3: Try to annotate locking contexts for sparse
v4: Reduce selftest lock duration to avoid a reset deadlock with fences
v5: s/srcu/reset_backoff_srcu/
v6: Remove more stale comments
Testcase: igt/gem_mmap_gtt/hang
Fixes: eb8d0f5af4 ("drm/i915: Remove GPU reset dependence on struct_mutex")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190208153708.20023-2-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
7ae1940014
commit
2caffbf117
@ -1280,14 +1280,11 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused)
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intel_wakeref_t wakeref;
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enum intel_engine_id id;
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seq_printf(m, "Reset flags: %lx\n", dev_priv->gpu_error.flags);
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if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
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seq_puts(m, "Wedged\n");
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seq_puts(m, "\tWedged\n");
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if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
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seq_puts(m, "Reset in progress: struct_mutex backoff\n");
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if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
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seq_puts(m, "Waiter holding struct mutex\n");
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if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
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seq_puts(m, "struct_mutex blocked for reset\n");
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seq_puts(m, "\tDevice (global) reset in progress\n");
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if (!i915_modparams.enable_hangcheck) {
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seq_puts(m, "Hangcheck disabled\n");
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@ -3872,9 +3869,6 @@ i915_wedged_set(void *data, u64 val)
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* while it is writing to 'i915_wedged'
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*/
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if (i915_reset_backoff(&i915->gpu_error))
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return -EAGAIN;
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i915_handle_error(i915, val, I915_ERROR_CAPTURE,
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"Manually set wedged engine mask = %llx", val);
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return 0;
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@ -3001,7 +3001,12 @@ i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
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i915_gem_object_unpin_pages(obj);
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}
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int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
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static inline int __must_check
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i915_mutex_lock_interruptible(struct drm_device *dev)
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{
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return mutex_lock_interruptible(&dev->struct_mutex);
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}
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int i915_gem_dumb_create(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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@ -3018,21 +3023,11 @@ int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
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struct i915_request *
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i915_gem_find_active_request(struct intel_engine_cs *engine);
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static inline bool i915_reset_backoff(struct i915_gpu_error *error)
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{
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return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
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}
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static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
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{
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return unlikely(test_bit(I915_WEDGED, &error->flags));
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}
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static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
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{
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return i915_reset_backoff(error) | i915_terminally_wedged(error);
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}
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static inline u32 i915_reset_count(struct i915_gpu_error *error)
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{
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return READ_ONCE(error->reset_count);
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@ -3105,7 +3100,6 @@ struct drm_i915_fence_reg *
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i915_reserve_fence(struct drm_i915_private *dev_priv);
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void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
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void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
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void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
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void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
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@ -98,47 +98,6 @@ static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
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spin_unlock(&dev_priv->mm.object_stat_lock);
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}
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static int
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i915_gem_wait_for_error(struct i915_gpu_error *error)
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{
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int ret;
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might_sleep();
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/*
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* Only wait 10 seconds for the gpu reset to complete to avoid hanging
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* userspace. If it takes that long something really bad is going on and
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* we should simply try to bail out and fail as gracefully as possible.
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*/
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ret = wait_event_interruptible_timeout(error->reset_queue,
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!i915_reset_backoff(error),
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I915_RESET_TIMEOUT);
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if (ret == 0) {
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DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
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return -EIO;
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} else if (ret < 0) {
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return ret;
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} else {
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return 0;
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}
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}
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int i915_mutex_lock_interruptible(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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int ret;
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ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
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if (ret)
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return ret;
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ret = mutex_lock_interruptible(&dev->struct_mutex);
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if (ret)
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return ret;
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return 0;
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}
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static u32 __i915_gem_park(struct drm_i915_private *i915)
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{
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intel_wakeref_t wakeref;
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@ -1885,6 +1844,7 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
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intel_wakeref_t wakeref;
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struct i915_vma *vma;
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pgoff_t page_offset;
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int srcu;
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int ret;
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/* Sanity check that we allow writing into this object */
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@ -1924,7 +1884,6 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
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goto err_unlock;
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}
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/* Now pin it into the GTT as needed */
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vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0,
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PIN_MAPPABLE |
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@ -1962,9 +1921,15 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
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if (ret)
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goto err_unpin;
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srcu = i915_reset_trylock(dev_priv);
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if (srcu < 0) {
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ret = srcu;
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goto err_unpin;
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}
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ret = i915_vma_pin_fence(vma);
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if (ret)
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goto err_unpin;
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goto err_reset;
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/* Finally, remap it using the new GTT offset */
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ret = remap_io_mapping(area,
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@ -1985,6 +1950,8 @@ vm_fault_t i915_gem_fault(struct vm_fault *vmf)
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err_fence:
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i915_vma_unpin_fence(vma);
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err_reset:
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i915_reset_unlock(dev_priv, srcu);
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err_unpin:
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__i915_vma_unpin(vma);
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err_unlock:
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@ -5342,6 +5309,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
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init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
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init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
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mutex_init(&dev_priv->gpu_error.wedge_mutex);
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init_srcu_struct(&dev_priv->gpu_error.reset_backoff_srcu);
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atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
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@ -5374,6 +5342,8 @@ void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
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GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
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WARN_ON(dev_priv->mm.object_count);
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cleanup_srcu_struct(&dev_priv->gpu_error.reset_backoff_srcu);
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kmem_cache_destroy(dev_priv->priorities);
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kmem_cache_destroy(dev_priv->dependencies);
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kmem_cache_destroy(dev_priv->requests);
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@ -270,6 +270,10 @@ static int fence_update(struct drm_i915_fence_reg *fence,
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return 0;
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}
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ret = i915_reset_trylock(fence->i915);
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if (ret < 0)
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goto out_rpm;
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fence_write(fence, vma);
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fence->vma = vma;
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@ -278,8 +282,12 @@ static int fence_update(struct drm_i915_fence_reg *fence,
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list_move_tail(&fence->link, &fence->i915->mm.fence_list);
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}
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i915_reset_unlock(fence->i915, ret);
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ret = 0;
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out_rpm:
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intel_runtime_pm_put(fence->i915, wakeref);
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return 0;
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return ret;
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}
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/**
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@ -442,32 +450,6 @@ void i915_unreserve_fence(struct drm_i915_fence_reg *fence)
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list_add(&fence->link, &fence->i915->mm.fence_list);
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}
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/**
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* i915_gem_revoke_fences - revoke fence state
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* @dev_priv: i915 device private
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*
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* Removes all GTT mmappings via the fence registers. This forces any user
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* of the fence to reacquire that fence before continuing with their access.
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* One use is during GPU reset where the fence register is lost and we need to
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* revoke concurrent userspace access via GTT mmaps until the hardware has been
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* reset and the fence registers have been restored.
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*/
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void i915_gem_revoke_fences(struct drm_i915_private *dev_priv)
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{
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int i;
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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for (i = 0; i < dev_priv->num_fence_regs; i++) {
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struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i];
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GEM_BUG_ON(fence->vma && fence->vma->fence != fence);
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if (fence->vma)
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i915_vma_revoke_mmap(fence->vma);
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}
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}
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/**
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* i915_gem_restore_fences - restore fence state
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* @dev_priv: i915 device private
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@ -204,39 +204,13 @@ struct i915_gpu_error {
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atomic_t pending_fb_pin;
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/**
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* State variable controlling the reset flow and count
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*
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* This is a counter which gets incremented when reset is triggered,
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*
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* Before the reset commences, the I915_RESET_BACKOFF bit is set
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* meaning that any waiters holding onto the struct_mutex should
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* relinquish the lock immediately in order for the reset to start.
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*
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* If reset is not completed successfully, the I915_WEDGE bit is
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* set meaning that hardware is terminally sour and there is no
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* recovery. All waiters on the reset_queue will be woken when
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* that happens.
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*
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* This counter is used by the wait_seqno code to notice that reset
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* event happened and it needs to restart the entire ioctl (since most
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* likely the seqno it waited for won't ever signal anytime soon).
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*
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* This is important for lock-free wait paths, where no contended lock
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* naturally enforces the correct ordering between the bail-out of the
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* waiter and the gpu reset work code.
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*/
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unsigned long reset_count;
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/**
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* flags: Control various stages of the GPU reset
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*
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* #I915_RESET_BACKOFF - When we start a reset, we want to stop any
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* other users acquiring the struct_mutex. To do this we set the
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* #I915_RESET_BACKOFF bit in the error flags when we detect a reset
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* and then check for that bit before acquiring the struct_mutex (in
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* i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
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* secondary role in preventing two concurrent global reset attempts.
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* #I915_RESET_BACKOFF - When we start a global reset, we need to
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* serialise with any other users attempting to do the same, and
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* any global resources that may be clobber by the reset (such as
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* FENCE registers).
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*
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* #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
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* acquire the struct_mutex to reset an engine, we need an explicit
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@ -255,6 +229,9 @@ struct i915_gpu_error {
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#define I915_RESET_ENGINE 2
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#define I915_WEDGED (BITS_PER_LONG - 1)
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/** Number of times the device has been reset (global) */
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u32 reset_count;
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/** Number of times an engine has been reset */
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u32 reset_engine_count[I915_NUM_ENGINES];
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@ -272,6 +249,8 @@ struct i915_gpu_error {
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*/
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wait_queue_head_t reset_queue;
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struct srcu_struct reset_backoff_srcu;
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struct i915_gpu_restart *restart;
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};
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@ -639,6 +639,32 @@ static void reset_prepare_engine(struct intel_engine_cs *engine)
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engine->reset.prepare(engine);
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}
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static void revoke_mmaps(struct drm_i915_private *i915)
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{
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int i;
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for (i = 0; i < i915->num_fence_regs; i++) {
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struct drm_vma_offset_node *node;
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struct i915_vma *vma;
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u64 vma_offset;
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vma = READ_ONCE(i915->fence_regs[i].vma);
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if (!vma)
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continue;
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if (!i915_vma_has_userfault(vma))
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continue;
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GEM_BUG_ON(vma->fence != &i915->fence_regs[i]);
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node = &vma->obj->base.vma_node;
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vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
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unmap_mapping_range(i915->drm.anon_inode->i_mapping,
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drm_vma_node_offset_addr(node) + vma_offset,
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vma->size,
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1);
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}
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}
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static void reset_prepare(struct drm_i915_private *i915)
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{
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struct intel_engine_cs *engine;
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@ -648,6 +674,7 @@ static void reset_prepare(struct drm_i915_private *i915)
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reset_prepare_engine(engine);
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intel_uc_sanitize(i915);
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revoke_mmaps(i915);
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}
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static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
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@ -911,50 +938,22 @@ unlock:
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return ret;
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}
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struct __i915_reset {
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struct drm_i915_private *i915;
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unsigned int stalled_mask;
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};
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static int __i915_reset__BKL(void *data)
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static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
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{
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struct __i915_reset *arg = data;
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int err;
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int err, i;
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err = intel_gpu_reset(arg->i915, ALL_ENGINES);
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/* Flush everyone currently using a resource about to be clobbered */
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synchronize_srcu(&i915->gpu_error.reset_backoff_srcu);
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err = intel_gpu_reset(i915, ALL_ENGINES);
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for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
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msleep(10 * (i + 1));
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err = intel_gpu_reset(i915, ALL_ENGINES);
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}
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if (err)
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return err;
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return gt_reset(arg->i915, arg->stalled_mask);
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}
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#if RESET_UNDER_STOP_MACHINE
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/*
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* XXX An alternative to using stop_machine would be to park only the
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* processes that have a GGTT mmap. By remote parking the threads (SIGSTOP)
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* we should be able to prevent their memmory accesses via the lost fence
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* registers over the course of the reset without the potential recursive
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* of mutexes between the pagefault handler and reset.
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*
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* See igt/gem_mmap_gtt/hang
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*/
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#define __do_reset(fn, arg) stop_machine(fn, arg, NULL)
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#else
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#define __do_reset(fn, arg) fn(arg)
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#endif
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static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
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{
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struct __i915_reset arg = { i915, stalled_mask };
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int err, i;
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err = __do_reset(__i915_reset__BKL, &arg);
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for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
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msleep(100);
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err = __do_reset(__i915_reset__BKL, &arg);
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}
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return err;
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return gt_reset(i915, stalled_mask);
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}
|
||||
|
||||
/**
|
||||
@ -966,8 +965,6 @@ static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask)
|
||||
* Reset the chip. Useful if a hang is detected. Marks the device as wedged
|
||||
* on failure.
|
||||
*
|
||||
* Caller must hold the struct_mutex.
|
||||
*
|
||||
* Procedure is fairly simple:
|
||||
* - reset the chip using the reset reg
|
||||
* - re-init context state
|
||||
@ -1274,9 +1271,12 @@ void i915_handle_error(struct drm_i915_private *i915,
|
||||
wait_event(i915->gpu_error.reset_queue,
|
||||
!test_bit(I915_RESET_BACKOFF,
|
||||
&i915->gpu_error.flags));
|
||||
goto out;
|
||||
goto out; /* piggy-back on the other reset */
|
||||
}
|
||||
|
||||
/* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
|
||||
synchronize_rcu_expedited();
|
||||
|
||||
/* Prevent any other reset-engine attempt. */
|
||||
for_each_engine(engine, i915, tmp) {
|
||||
while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
|
||||
@ -1300,6 +1300,36 @@ out:
|
||||
intel_runtime_pm_put(i915, wakeref);
|
||||
}
|
||||
|
||||
int i915_reset_trylock(struct drm_i915_private *i915)
|
||||
{
|
||||
struct i915_gpu_error *error = &i915->gpu_error;
|
||||
int srcu;
|
||||
|
||||
rcu_read_lock();
|
||||
while (test_bit(I915_RESET_BACKOFF, &error->flags)) {
|
||||
rcu_read_unlock();
|
||||
|
||||
if (wait_event_interruptible(error->reset_queue,
|
||||
!test_bit(I915_RESET_BACKOFF,
|
||||
&error->flags)))
|
||||
return -EINTR;
|
||||
|
||||
rcu_read_lock();
|
||||
}
|
||||
srcu = srcu_read_lock(&error->reset_backoff_srcu);
|
||||
rcu_read_unlock();
|
||||
|
||||
return srcu;
|
||||
}
|
||||
|
||||
void i915_reset_unlock(struct drm_i915_private *i915, int tag)
|
||||
__releases(&i915->gpu_error.reset_backoff_srcu)
|
||||
{
|
||||
struct i915_gpu_error *error = &i915->gpu_error;
|
||||
|
||||
srcu_read_unlock(&error->reset_backoff_srcu, tag);
|
||||
}
|
||||
|
||||
bool i915_reset_flush(struct drm_i915_private *i915)
|
||||
{
|
||||
int err;
|
||||
|
||||
@ -9,6 +9,7 @@
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/srcu.h>
|
||||
|
||||
struct drm_i915_private;
|
||||
struct intel_engine_cs;
|
||||
@ -32,6 +33,9 @@ int i915_reset_engine(struct intel_engine_cs *engine,
|
||||
void i915_reset_request(struct i915_request *rq, bool guilty);
|
||||
bool i915_reset_flush(struct drm_i915_private *i915);
|
||||
|
||||
int __must_check i915_reset_trylock(struct drm_i915_private *i915);
|
||||
void i915_reset_unlock(struct drm_i915_private *i915, int tag);
|
||||
|
||||
bool intel_has_gpu_reset(struct drm_i915_private *i915);
|
||||
bool intel_has_reset_engine(struct drm_i915_private *i915);
|
||||
|
||||
|
||||
@ -995,9 +995,6 @@ struct intel_crtc {
|
||||
|
||||
struct intel_crtc_state *config;
|
||||
|
||||
/* global reset count when the last flip was submitted */
|
||||
unsigned int reset_count;
|
||||
|
||||
/* Access to these should be protected by dev_priv->irq_lock. */
|
||||
bool cpu_fifo_underrun_disabled;
|
||||
bool pch_fifo_underrun_disabled;
|
||||
|
||||
@ -1039,8 +1039,6 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915,
|
||||
|
||||
/* Check that we can recover an unbind stuck on a hanging request */
|
||||
|
||||
igt_global_reset_lock(i915);
|
||||
|
||||
mutex_lock(&i915->drm.struct_mutex);
|
||||
err = hang_init(&h, i915);
|
||||
if (err)
|
||||
@ -1138,7 +1136,9 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915,
|
||||
}
|
||||
|
||||
out_reset:
|
||||
igt_global_reset_lock(i915);
|
||||
fake_hangcheck(rq->i915, intel_engine_flag(rq->engine));
|
||||
igt_global_reset_unlock(i915);
|
||||
|
||||
if (tsk) {
|
||||
struct igt_wedge_me w;
|
||||
@ -1159,7 +1159,6 @@ fini:
|
||||
hang_fini(&h);
|
||||
unlock:
|
||||
mutex_unlock(&i915->drm.struct_mutex);
|
||||
igt_global_reset_unlock(i915);
|
||||
|
||||
if (i915_terminally_wedged(&i915->gpu_error))
|
||||
return -EIO;
|
||||
|
||||
@ -189,6 +189,7 @@ struct drm_i915_private *mock_gem_device(void)
|
||||
|
||||
init_waitqueue_head(&i915->gpu_error.wait_queue);
|
||||
init_waitqueue_head(&i915->gpu_error.reset_queue);
|
||||
init_srcu_struct(&i915->gpu_error.reset_backoff_srcu);
|
||||
mutex_init(&i915->gpu_error.wedge_mutex);
|
||||
|
||||
i915->wq = alloc_ordered_workqueue("mock", 0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user