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r8169: fix Config2 MSIEnable bit setting.
The MSIEnable bit is only available for the 8169. Avoid Config2 writes for the post-8169 8168 and 810x. Reported-by: Su Kang Yin <cantona@cantona.net> Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -477,7 +477,6 @@ enum rtl_register_content {
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/* Config1 register p.24 */
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LEDS1 = (1 << 7),
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LEDS0 = (1 << 6),
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MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
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Speed_down = (1 << 4),
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MEMMAP = (1 << 3),
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IOMAP = (1 << 2),
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@ -485,6 +484,7 @@ enum rtl_register_content {
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PMEnable = (1 << 0), /* Power Management Enable */
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/* Config2 register p. 25 */
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MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
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PCI_Clock_66MHz = 0x01,
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PCI_Clock_33MHz = 0x00,
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@ -3426,22 +3426,24 @@ static const struct rtl_cfg_info {
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};
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/* Cfg9346_Unlock assumed. */
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static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
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static unsigned rtl_try_msi(struct rtl8169_private *tp,
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const struct rtl_cfg_info *cfg)
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{
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void __iomem *ioaddr = tp->mmio_addr;
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unsigned msi = 0;
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u8 cfg2;
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cfg2 = RTL_R8(Config2) & ~MSIEnable;
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if (cfg->features & RTL_FEATURE_MSI) {
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if (pci_enable_msi(pdev)) {
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dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
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if (pci_enable_msi(tp->pci_dev)) {
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netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
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} else {
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cfg2 |= MSIEnable;
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msi = RTL_FEATURE_MSI;
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}
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}
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RTL_W8(Config2, cfg2);
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if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
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RTL_W8(Config2, cfg2);
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return msi;
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}
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@ -4077,7 +4079,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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tp->features |= RTL_FEATURE_WOL;
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if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
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tp->features |= RTL_FEATURE_WOL;
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tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
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tp->features |= rtl_try_msi(tp, cfg);
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RTL_W8(Cfg9346, Cfg9346_Lock);
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if (rtl_tbi_enabled(tp)) {
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