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clk: stm32mp1: add RTC clock
This patch adds the RTC clock. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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@ -248,6 +248,10 @@ static const char * const dsi_src[] = {
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"ck_dsi_phy", "pll4_p"
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"ck_dsi_phy", "pll4_p"
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};
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};
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static const char * const rtc_src[] = {
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"off", "ck_lse", "ck_lsi", "ck_hse_rtc"
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};
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static const struct clk_div_table axi_div_table[] = {
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static const struct clk_div_table axi_div_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
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{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
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{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
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{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
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@ -1945,6 +1949,17 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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_NO_GATE,
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_NO_GATE,
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_MMUX(M_ETHCK),
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_MMUX(M_ETHCK),
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_DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
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_DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
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/* RTC clock */
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DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
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CLK_DIVIDER_ALLOW_ZERO),
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COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
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CLK_SET_RATE_PARENT,
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_GATE(RCC_BDCR, 20, 0),
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_MUX(RCC_BDCR, 16, 2, 0),
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_NO_DIV),
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};
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};
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struct stm32_clock_match_data {
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struct stm32_clock_match_data {
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