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usb: dwc3: add definitions for new registers
This patch adds definitions for some new registers that have been added to later versions of the controller, up to v2.10a. Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Paul Zimmerman
Felipe Balbi
parent
a092532483
commit
2c61a8efce
@ -67,6 +67,7 @@
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#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
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#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
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#define DWC3_DEVICE_EVENT_WAKEUP 4
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#define DWC3_DEVICE_EVENT_HIBER_REQ 5
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#define DWC3_DEVICE_EVENT_EOPF 6
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#define DWC3_DEVICE_EVENT_SOF 7
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#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
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@ -171,28 +172,36 @@
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#define DWC3_GCTL_PRTCAP_DEVICE 2
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#define DWC3_GCTL_PRTCAP_OTG 3
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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#define DWC3_GCTL_CORESOFTRESET (1 << 11)
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#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
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#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
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#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
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#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
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/* Global USB2 PHY Configuration Register */
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
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/* Global USB3 PIPE Control Register */
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
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#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
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/* Global TX Fifo Size Register */
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#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
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#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
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#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
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#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
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/* Global HWPARAMS1 Register */
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#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
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#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
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#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
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#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
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#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
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#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
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/* Global HWPARAMS4 Register */
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#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
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#define DWC3_MAX_HIBER_SCRATCHBUFS 15
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/* Device Configuration Register */
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#define DWC3_DCFG_LPM_CAP (1 << 22)
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@ -206,6 +215,8 @@
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#define DWC3_DCFG_LOWSPEED (2 << 0)
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#define DWC3_DCFG_FULLSPEED1 (3 << 0)
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#define DWC3_DCFG_LPM_CAP (1 << 22)
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/* Device Control Register */
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#define DWC3_DCTL_RUN_STOP (1 << 31)
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#define DWC3_DCTL_CSFTRST (1 << 30)
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@ -216,14 +227,20 @@
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#define DWC3_DCTL_APPL1RES (1 << 23)
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#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
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#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
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/* These apply for core versions 1.87a and earlier */
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#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
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#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
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#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
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#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
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#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
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#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
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#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
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#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
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#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
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#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
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#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
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#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
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/* These apply for core versions 1.94a and later */
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#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
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#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
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#define DWC3_DCTL_CRS (1 << 17)
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#define DWC3_DCTL_CSS (1 << 16)
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#define DWC3_DCTL_INITU2ENA (1 << 12)
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#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
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@ -249,6 +266,7 @@
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#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
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#define DWC3_DEVTEN_SOFEN (1 << 7)
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#define DWC3_DEVTEN_EOPFEN (1 << 6)
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#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
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#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
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#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
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#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
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@ -256,7 +274,15 @@
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#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
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/* Device Status Register */
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#define DWC3_DSTS_DCNRD (1 << 29)
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/* This applies for core versions 1.87a and earlier */
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#define DWC3_DSTS_PWRUPREQ (1 << 24)
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/* These apply for core versions 1.94a and later */
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#define DWC3_DSTS_RSS (1 << 25)
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#define DWC3_DSTS_SSS (1 << 24)
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#define DWC3_DSTS_COREIDLE (1 << 23)
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#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
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@ -280,6 +306,11 @@
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#define DWC3_DGCMD_SET_LMP 0x01
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#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
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#define DWC3_DGCMD_XMIT_FUNCTION 0x03
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/* These apply for core versions 1.94a and later */
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#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
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#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
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#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
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#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
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#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
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@ -287,6 +318,15 @@
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#define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
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#define DWC3_DGCMD_CMDACT (1 << 10)
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#define DWC3_DGCMD_CMDIOC (1 << 8)
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/* Device Generic Command Parameter Register */
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#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
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#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
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#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
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#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
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#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
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#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
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/* Device Endpoint Command Register */
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#define DWC3_DEPCMD_PARAM_SHIFT 16
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@ -303,7 +343,10 @@
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#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
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#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
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#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
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/* This applies for core versions 1.90a and earlier */
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#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
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/* This applies for core versions 1.94a and later */
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#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
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#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
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#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
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@ -437,6 +480,8 @@ enum dwc3_link_state {
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DWC3_LINK_STATE_HRESET = 0x09,
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DWC3_LINK_STATE_CMPLY = 0x0a,
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DWC3_LINK_STATE_LPBK = 0x0b,
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DWC3_LINK_STATE_RESET = 0x0e,
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DWC3_LINK_STATE_RESUME = 0x0f,
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DWC3_LINK_STATE_MASK = 0x0f,
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};
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@ -455,6 +500,7 @@ enum dwc3_device_state {
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#define DWC3_TRBSTS_OK 0
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#define DWC3_TRBSTS_MISSED_ISOC 1
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#define DWC3_TRBSTS_SETUP_PENDING 2
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#define DWC3_TRB_STS_XFER_IN_PROG 4
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/* TRB Control */
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#define DWC3_TRB_CTRL_HWO (1 << 0)
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@ -543,6 +589,14 @@ struct dwc3_request {
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unsigned queued:1;
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};
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/*
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* struct dwc3_scratchpad_array - hibernation scratchpad array
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* (format defined by hw)
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*/
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struct dwc3_scratchpad_array {
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__le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
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};
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/**
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* struct dwc3 - representation of our controller
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* @ctrl_req: usb control request which is used for ep0
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@ -624,8 +678,10 @@ struct dwc3 {
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#define DWC3_REVISION_180A 0x5533180a
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#define DWC3_REVISION_183A 0x5533183a
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#define DWC3_REVISION_185A 0x5533185a
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#define DWC3_REVISION_187A 0x5533187a
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#define DWC3_REVISION_188A 0x5533188a
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#define DWC3_REVISION_190A 0x5533190a
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#define DWC3_REVISION_194A 0x5533194a
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#define DWC3_REVISION_200A 0x5533200a
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#define DWC3_REVISION_202A 0x5533202a
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#define DWC3_REVISION_210A 0x5533210a
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@ -66,7 +66,12 @@ struct dwc3;
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#define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
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#define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22)
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#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
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/* This applies for core versions earlier than 1.94a */
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#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
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/* These apply for core versions 1.94a and later */
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#define DWC3_DEPCFG_ACTION_INIT (0 << 30)
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#define DWC3_DEPCFG_ACTION_RESTORE (1 << 30)
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#define DWC3_DEPCFG_ACTION_MODIFY (2 << 30)
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/* DEPXFERCFG parameter 0 */
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#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
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