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davinci: EDMA: add support for dm646x

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Enables module clock for DM646x EDMA channel controller and transfer
controller.

Signed-off-by: Naresh Medisetty <naresh@ti.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Sudhakar Rajashekhara 2009-06-02 03:38:26 -04:00 committed by Kevin Hilman
parent 60902a2cb1
commit 2bcb613a79
1 changed files with 40 additions and 0 deletions
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40
arch/arm/mach-davinci/dm646x.c
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@ -162,6 +162,41 @@ static struct clk arm_clk = {
.flags = ALWAYS_ENABLED, .flags = ALWAYS_ENABLED,
}; };
static struct clk edma_cc_clk = {
.name = "edma_cc",
.parent = &pll1_sysclk2,
.lpsc = DM646X_LPSC_TPCC,
.flags = ALWAYS_ENABLED,
};
static struct clk edma_tc0_clk = {
.name = "edma_tc0",
.parent = &pll1_sysclk2,
.lpsc = DM646X_LPSC_TPTC0,
.flags = ALWAYS_ENABLED,
};
static struct clk edma_tc1_clk = {
.name = "edma_tc1",
.parent = &pll1_sysclk2,
.lpsc = DM646X_LPSC_TPTC1,
.flags = ALWAYS_ENABLED,
};
static struct clk edma_tc2_clk = {
.name = "edma_tc2",
.parent = &pll1_sysclk2,
.lpsc = DM646X_LPSC_TPTC2,
.flags = ALWAYS_ENABLED,
};
static struct clk edma_tc3_clk = {
.name = "edma_tc3",
.parent = &pll1_sysclk2,
.lpsc = DM646X_LPSC_TPTC3,
.flags = ALWAYS_ENABLED,
};
static struct clk uart0_clk = { static struct clk uart0_clk = {
.name = "uart0", .name = "uart0",
.parent = &aux_clkin, .parent = &aux_clkin,
@ -269,6 +304,11 @@ struct davinci_clk dm646x_clks[] = {
CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
CLK(NULL, "dsp", &dsp_clk), CLK(NULL, "dsp", &dsp_clk),
CLK(NULL, "arm", &arm_clk), CLK(NULL, "arm", &arm_clk),
CLK(NULL, "edma_cc", &edma_cc_clk),
CLK(NULL, "edma_tc0", &edma_tc0_clk),
CLK(NULL, "edma_tc1", &edma_tc1_clk),
CLK(NULL, "edma_tc2", &edma_tc2_clk),
CLK(NULL, "edma_tc3", &edma_tc3_clk),
CLK(NULL, "uart0", &uart0_clk), CLK(NULL, "uart0", &uart0_clk),
CLK(NULL, "uart1", &uart1_clk), CLK(NULL, "uart1", &uart1_clk),
CLK(NULL, "uart2", &uart2_clk), CLK(NULL, "uart2", &uart2_clk),