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Staging: vme: Add location monitor support for ca91cx42
Signed-off-by: Martyn Welch <martyn.welch@ge.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Martyn Welch
Greg Kroah-Hartman
parent
8fafb47638
commit
2b82beb8c1
@ -58,7 +58,6 @@ Universe II (ca91c142)
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- DMA unsupported.
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- RMW transactions unsupported.
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- Location Monitors unsupported.
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- Mailboxes unsupported.
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- Error Detection.
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- Control of prefetch size, threshold.
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@ -899,6 +899,206 @@ ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
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return retval;
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}
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/*
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* All 4 location monitors reside at the same base - this is therefore a
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* system wide configuration.
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*
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* This does not enable the LM monitor - that should be done when the first
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* callback is attached and disabled when the last callback is removed.
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*/
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int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
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vme_address_t aspace, vme_cycle_t cycle)
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{
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u32 temp_base, lm_ctl = 0;
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int i;
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struct ca91cx42_driver *bridge;
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struct device *dev;
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bridge = lm->parent->driver_priv;
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dev = lm->parent->parent;
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/* Check the alignment of the location monitor */
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temp_base = (u32)lm_base;
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if (temp_base & 0xffff) {
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dev_err(dev, "Location monitor must be aligned to 64KB "
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"boundary");
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return -EINVAL;
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}
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mutex_lock(&(lm->mtx));
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/* If we already have a callback attached, we can't move it! */
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for (i = 0; i < lm->monitors; i++) {
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if (bridge->lm_callback[i] != NULL) {
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mutex_unlock(&(lm->mtx));
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dev_err(dev, "Location monitor callback attached, "
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"can't reset\n");
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return -EBUSY;
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}
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}
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switch (aspace) {
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case VME_A16:
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lm_ctl |= CA91CX42_LM_CTL_AS_A16;
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break;
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case VME_A24:
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lm_ctl |= CA91CX42_LM_CTL_AS_A24;
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break;
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case VME_A32:
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lm_ctl |= CA91CX42_LM_CTL_AS_A32;
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break;
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default:
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mutex_unlock(&(lm->mtx));
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dev_err(dev, "Invalid address space\n");
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return -EINVAL;
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break;
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}
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if (cycle & VME_SUPER)
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lm_ctl |= CA91CX42_LM_CTL_SUPR;
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if (cycle & VME_USER)
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lm_ctl |= CA91CX42_LM_CTL_NPRIV;
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if (cycle & VME_PROG)
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lm_ctl |= CA91CX42_LM_CTL_PGM;
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if (cycle & VME_DATA)
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lm_ctl |= CA91CX42_LM_CTL_DATA;
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iowrite32(lm_base, bridge->base + LM_BS);
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iowrite32(lm_ctl, bridge->base + LM_CTL);
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mutex_unlock(&(lm->mtx));
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return 0;
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}
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/* Get configuration of the callback monitor and return whether it is enabled
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* or disabled.
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*/
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int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
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vme_address_t *aspace, vme_cycle_t *cycle)
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{
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u32 lm_ctl, enabled = 0;
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struct ca91cx42_driver *bridge;
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bridge = lm->parent->driver_priv;
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mutex_lock(&(lm->mtx));
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*lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
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lm_ctl = ioread32(bridge->base + LM_CTL);
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if (lm_ctl & CA91CX42_LM_CTL_EN)
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enabled = 1;
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if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
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*aspace = VME_A16;
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if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
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*aspace = VME_A24;
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if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
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*aspace = VME_A32;
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*cycle = 0;
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if (lm_ctl & CA91CX42_LM_CTL_SUPR)
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*cycle |= VME_SUPER;
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if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
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*cycle |= VME_USER;
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if (lm_ctl & CA91CX42_LM_CTL_PGM)
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*cycle |= VME_PROG;
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if (lm_ctl & CA91CX42_LM_CTL_DATA)
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*cycle |= VME_DATA;
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mutex_unlock(&(lm->mtx));
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return enabled;
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}
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/*
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* Attach a callback to a specific location monitor.
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*
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* Callback will be passed the monitor triggered.
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*/
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int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
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void (*callback)(int))
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{
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u32 lm_ctl, tmp;
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struct ca91cx42_driver *bridge;
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struct device *dev;
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bridge = lm->parent->driver_priv;
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dev = lm->parent->parent;
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mutex_lock(&(lm->mtx));
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/* Ensure that the location monitor is configured - need PGM or DATA */
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lm_ctl = ioread32(bridge->base + LM_CTL);
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if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
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mutex_unlock(&(lm->mtx));
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dev_err(dev, "Location monitor not properly configured\n");
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return -EINVAL;
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}
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/* Check that a callback isn't already attached */
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if (bridge->lm_callback[monitor] != NULL) {
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mutex_unlock(&(lm->mtx));
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dev_err(dev, "Existing callback attached\n");
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return -EBUSY;
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}
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/* Attach callback */
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bridge->lm_callback[monitor] = callback;
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/* Enable Location Monitor interrupt */
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tmp = ioread32(bridge->base + LINT_EN);
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tmp |= CA91CX42_LINT_LM[monitor];
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iowrite32(tmp, bridge->base + LINT_EN);
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/* Ensure that global Location Monitor Enable set */
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if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
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lm_ctl |= CA91CX42_LM_CTL_EN;
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iowrite32(lm_ctl, bridge->base + LM_CTL);
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}
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mutex_unlock(&(lm->mtx));
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return 0;
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}
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/*
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* Detach a callback function forn a specific location monitor.
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*/
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int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
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{
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u32 tmp;
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struct ca91cx42_driver *bridge;
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bridge = lm->parent->driver_priv;
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mutex_lock(&(lm->mtx));
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/* Disable Location Monitor and ensure previous interrupts are clear */
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tmp = ioread32(bridge->base + LINT_EN);
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tmp &= ~CA91CX42_LINT_LM[monitor];
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iowrite32(tmp, bridge->base + LINT_EN);
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iowrite32(CA91CX42_LINT_LM[monitor],
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bridge->base + LINT_STAT);
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/* Detach callback */
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bridge->lm_callback[monitor] = NULL;
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/* If all location monitors disabled, disable global Location Monitor */
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if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
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CA91CX42_LINT_LM3)) == 0) {
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tmp = ioread32(bridge->base + LM_CTL);
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tmp &= ~CA91CX42_LM_CTL_EN;
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iowrite32(tmp, bridge->base + LM_CTL);
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}
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mutex_unlock(&(lm->mtx));
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return 0;
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}
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int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
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{
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u32 slot = 0;
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@ -1190,12 +1390,10 @@ static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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#endif
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ca91cx42_bridge->irq_set = ca91cx42_irq_set;
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ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
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#if 0
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ca91cx42_bridge->lm_set = ca91cx42_lm_set;
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ca91cx42_bridge->lm_get = ca91cx42_lm_get;
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ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
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ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
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#endif
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ca91cx42_bridge->slot_get = ca91cx42_slot_get;
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data = ioread32(ca91cx42_device->base + MISC_CTL);
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@ -1786,77 +1984,7 @@ int ca91cx42_do_dma(vmeDmaPacket_t *vmeDma)
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return 0;
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}
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int ca91cx42_lm_set(vmeLmCfg_t *vmeLm)
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{
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int temp_ctl = 0;
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if (vmeLm->addrU)
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return -EINVAL;
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switch (vmeLm->addrSpace) {
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case VME_A64:
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case VME_USER3:
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case VME_USER4:
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return -EINVAL;
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case VME_A16:
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temp_ctl |= 0x00000;
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break;
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case VME_A24:
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temp_ctl |= 0x10000;
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break;
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case VME_A32:
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temp_ctl |= 0x20000;
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break;
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case VME_CRCSR:
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temp_ctl |= 0x50000;
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break;
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case VME_USER1:
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temp_ctl |= 0x60000;
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break;
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case VME_USER2:
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temp_ctl |= 0x70000;
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break;
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}
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/* Disable while we are mucking around */
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iowrite32(0x00000000, bridge->base + LM_CTL);
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iowrite32(vmeLm->addr, bridge->base + LM_BS);
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/* Setup CTL register. */
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if (vmeLm->userAccessType & VME_SUPER)
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temp_ctl |= 0x00200000;
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if (vmeLm->userAccessType & VME_USER)
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temp_ctl |= 0x00100000;
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if (vmeLm->dataAccessType & VME_PROG)
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temp_ctl |= 0x00800000;
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if (vmeLm->dataAccessType & VME_DATA)
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temp_ctl |= 0x00400000;
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/* Write ctl reg and enable */
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iowrite32(0x80000000 | temp_ctl, bridge->base + LM_CTL);
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temp_ctl = ioread32(bridge->base + LM_CTL);
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return 0;
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}
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int ca91cx42_wait_lm(vmeLmCfg_t *vmeLm)
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{
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unsigned long flags;
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unsigned int tmp;
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spin_lock_irqsave(&lm_lock, flags);
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spin_unlock_irqrestore(&lm_lock, flags);
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if (tmp == 0) {
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if (vmeLm->lmWait < 10)
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vmeLm->lmWait = 10;
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interruptible_sleep_on_timeout(&lm_queue, vmeLm->lmWait);
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}
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iowrite32(0x00000000, bridge->base + LM_CTL);
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return 0;
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}
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@ -491,6 +491,19 @@ static const int CA91CX42_LINT_LM[] = { CA91CX42_LINT_LM0, CA91CX42_LINT_LM1,
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#define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0)
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#define CA91CX42_VSI_CTL_LAS_PCI_CONF (1<<1)
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/* LM_CTL Register
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* offset F64
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*/
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#define CA91CX42_LM_CTL_EN (1<<31)
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#define CA91CX42_LM_CTL_PGM (1<<23)
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#define CA91CX42_LM_CTL_DATA (1<<22)
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#define CA91CX42_LM_CTL_SUPR (1<<21)
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#define CA91CX42_LM_CTL_NPRIV (1<<20)
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#define CA91CX42_LM_CTL_AS_M (5<<16)
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#define CA91CX42_LM_CTL_AS_A16 0
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#define CA91CX42_LM_CTL_AS_A24 (1<<16)
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#define CA91CX42_LM_CTL_AS_A32 (1<<17)
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/*
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* VRAI_CTL Register
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* offset F70
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