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arm64: dts: sprd: Add support for Unisoc's UMS512
Add basic support for Unisoc's UMS512, with this patch, the board ums512-1h10 can run into console. Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Link: https://lore.kernel.org/r/20230306085717.420353-1-chunyan.zhang@unisoc.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Chunyan Zhang
Arnd Bergmann
parent
129469c488
commit
2b4881839a
@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
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sp9860g-1h10.dtb \
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sp9863a-1h10.dtb
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sp9863a-1h10.dtb \
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ums512-1h10.dtb
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61
arch/arm64/boot/dts/sprd/ums512-1h10.dts
Normal file
61
arch/arm64/boot/dts/sprd/ums512-1h10.dts
Normal file
@ -0,0 +1,61 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Unisoc UMS512-1h10 boards DTS file
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*
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* Copyright (C) 2021, Unisoc Inc.
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*/
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/dts-v1/;
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#include "ums512.dtsi"
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/ {
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model = "Unisoc UMS512-1H10 Board";
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compatible = "sprd,ums512-1h10", "sprd,ums512";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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chosen {
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stdout-path = "serial1:115200n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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/* SD card */
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&sdio0 {
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bus-width = <4>;
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no-sdio;
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no-mmc;
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sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>;
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sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>;
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sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>;
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sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>;
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sd-uhs-sdr104;
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sd-uhs-sdr50;
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};
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/* EMMC storage */
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&sdio3 {
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status = "okay";
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bus-width = <8>;
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no-sdio;
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no-sd;
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non-removable;
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cap-mmc-hw-reset;
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};
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911
arch/arm64/boot/dts/sprd/ums512.dtsi
Normal file
911
arch/arm64/boot/dts/sprd/ums512.dtsi
Normal file
@ -0,0 +1,911 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Unisoc UMS512 SoC DTS file
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*
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* Copyright (C) 2021, Unisoc Inc.
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*/
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#include <dt-bindings/clock/sprd,ums512-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD>;
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};
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};
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idle-states {
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entry-method = "psci";
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CORE_PD: core-pd {
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compatible = "arm,idle-state";
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entry-latency-us = <4000>;
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exit-latency-us = <4000>;
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min-residency-us = <10000>;
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local-timer-stop;
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arm,psci-suspend-param = <0x00010000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@12000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x12000000 0 0x20000>, /* GICD */
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<0x0 0x12040000 0 0x100000>; /* GICR */
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#interrupt-cells = <3>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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redistributor-stride = <0x0 0x20000>; /* 128KB stride */
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#redistributor-regions = <1>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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ap_ahb_regs: syscon@20100000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x20100000 0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x20100000 0x4000>;
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apahb_gate: clock-controller@0 {
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compatible = "sprd,ums512-apahb-gate";
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reg = <0x0 0x3000>;
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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};
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pub_apb_regs: syscon@31050000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x31050000 0 0x9000>;
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};
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top_dvfs_apb_regs: syscon@322a0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x322a0000 0 0x8000>;
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};
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ap_intc0_regs: syscon@32310000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32310000 0 0x1000>;
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};
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ap_intc1_regs: syscon@32320000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32320000 0 0x1000>;
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};
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ap_intc2_regs: syscon@32330000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32330000 0 0x1000>;
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};
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ap_intc3_regs: syscon@32340000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32340000 0 0x1000>;
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};
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ap_intc4_regs: syscon@32350000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32350000 0 0x1000>;
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};
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ap_intc5_regs: syscon@32360000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32360000 0 0x1000>;
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};
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anlg_phy_g0_regs: syscon@32390000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x32390000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x32390000 0x3000>;
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dpll0: clock-controller@0 {
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compatible = "sprd,ums512-g0-pll";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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};
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};
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anlg_phy_g2_regs: syscon@323b0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x323b0000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x323b0000 0x3000>;
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mpll1: clock-controller@0 {
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compatible = "sprd,ums512-g2-pll";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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};
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};
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anlg_phy_g3_regs: syscon@323c0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x323c0000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x323c0000 0x3000>;
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pll1: clock-controller@0 {
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compatible = "sprd,ums512-g3-pll";
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reg = <0x0 0x3000>;
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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};
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anlg_phy_gc_regs: syscon@323e0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x323e0000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x323e0000 0x3000>;
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pll2: clock-controller@0 {
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compatible = "sprd,ums512-gc-pll";
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reg = <0x0 0x100>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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};
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anlg_phy_g10_regs: syscon@323f0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x323f0000 0 0x3000>;
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};
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aon_apb_regs: syscon@327d0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x327d0000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x327d0000 0x3000>;
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aonapb_gate: clock-controller@0 {
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compatible = "sprd,ums512-aon-gate";
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reg = <0x0 0x3000>;
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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};
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pmu_apb_regs: syscon@327e0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x327e0000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x327e0000 0x3000>;
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pmu_gate: clock-controller@0 {
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compatible = "sprd,ums512-pmu-gate";
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reg = <0x0 0x3000>;
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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#clock-cells = <1>;
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};
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};
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audcp_apb_regs: syscon@3350d000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x3350d000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x3350d000 0x1000>;
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audcpapb_gate: clock-controller@0 {
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compatible = "sprd,ums512-audcpapb-gate";
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reg = <0x0 0x300>;
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#clock-cells = <1>;
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};
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};
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audcp_ahb_regs: syscon@335e0000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x335e0000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x335e0000 0x1000>;
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audcpahb_gate: clock-controller@0 {
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compatible = "sprd,ums512-audcpahb-gate";
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reg = <0x0 0x300>;
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#clock-cells = <1>;
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};
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};
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gpu_apb_regs: syscon@60100000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x60100000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x60100000 0x3000>;
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gpu_clk: clock-controller@0 {
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compatible = "sprd,ums512-gpu-clk";
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clocks = <&ext_26m>;
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clock-names = "ext-26m";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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};
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};
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gpu_dvfs_apb_regs: syscon@60110000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x60110000 0 0x3000>;
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};
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mm_ahb_regs: syscon@62200000 {
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compatible = "sprd,ums512-glbregs", "syscon",
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"simple-mfd";
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reg = <0 0x62200000 0 0x3000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x62200000 0x3000>;
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|
||||
mm_gate: clock-controller@0 {
|
||||
compatible = "sprd,ums512-mm-gate-clk";
|
||||
reg = <0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ap_apb_regs: syscon@71000000 {
|
||||
compatible = "sprd,ums512-glbregs", "syscon",
|
||||
"simple-mfd";
|
||||
reg = <0 0x71000000 0 0x3000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x71000000 0x3000>;
|
||||
|
||||
apapb_gate: clock-controller@0 {
|
||||
compatible = "sprd,ums512-apapb-gate";
|
||||
reg = <0x0 0x3000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ap_clk: clock-controller@20200000 {
|
||||
compatible = "sprd,ums512-ap-clk";
|
||||
reg = <0 0x20200000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "ext-26m";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
aon_clk: clock-controller@32080000 {
|
||||
compatible = "sprd,ums512-aonapb-clk";
|
||||
reg = <0 0x32080000 0 0x1000>;
|
||||
clocks = <&ext_26m>, <&ext_32k>,
|
||||
<&ext_4m>, <&rco_100m>;
|
||||
clock-names = "ext-26m", "ext-32k",
|
||||
"ext-4m", "rco-100m";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mm_clk: clock-controller@62100000 {
|
||||
compatible = "sprd,ums512-mm-clk";
|
||||
reg = <0 0x62100000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "ext-26m";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
/* SoC Funnel */
|
||||
funnel@3c002000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x3c002000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel_soc_out_port: endpoint {
|
||||
remote-endpoint = <&etb_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_soc_in_port: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_corinth_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SoC ETF */
|
||||
soc_etb: etb@3c003000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x3c003000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
etb_in: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_soc_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AP-CPU Funnel for core3/4/5/7 */
|
||||
funnel@3e001000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x3e001000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel_corinth_lit_out_port: endpoint {
|
||||
remote-endpoint =
|
||||
<&corinth_etf_lit_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_core_in_port3: endpoint {
|
||||
remote-endpoint = <&etm3_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_core_in_port4: endpoint {
|
||||
remote-endpoint = <&etm4_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel_core_in_port5: endpoint {
|
||||
remote-endpoint = <&etm5_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
funnel_core_in_port7: endpoint {
|
||||
remote-endpoint = <&etm7_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AP-CPU ETF for little cores */
|
||||
etf@3e002000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x3e002000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
corinth_etf_lit_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_corinth_from_lit_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
corinth_etf_lit_in: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_corinth_lit_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AP-CPU ETF for big cores */
|
||||
etf@3e003000 {
|
||||
compatible = "arm,coresight-tmc", "arm,primecell";
|
||||
reg = <0 0x3e003000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
corinth_etf_big_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_corinth_from_big_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
port {
|
||||
corinth_etf_big_in: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_corinth_big_out_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Funnel to SoC */
|
||||
funnel@3e004000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x3e004000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel_corinth_out_port: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_soc_in_port>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_corinth_from_lit_in_port: endpoint {
|
||||
remote-endpoint = <&corinth_etf_lit_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_corinth_from_big_in_port: endpoint {
|
||||
remote-endpoint = <&corinth_etf_big_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AP-CPU Funnel for core0/1/2/6 */
|
||||
funnel@3e005000 {
|
||||
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
|
||||
reg = <0 0x3e005000 0 0x1000>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
funnel_corinth_big_out_port: endpoint {
|
||||
remote-endpoint = <&corinth_etf_big_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
in-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
funnel_core_in_port0: endpoint {
|
||||
remote-endpoint = <&etm0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
funnel_core_in_port1: endpoint {
|
||||
remote-endpoint = <&etm1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
funnel_core_in_port2: endpoint {
|
||||
remote-endpoint = <&etm2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
funnel_core_in_port6: endpoint {
|
||||
remote-endpoint = <&etm6_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm0: etm@3f040000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f040000 0 0x1000>;
|
||||
cpu = <&CPU0>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm0_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm1: etm@3f140000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f140000 0 0x1000>;
|
||||
cpu = <&CPU1>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm1_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm2: etm@3f240000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f240000 0 0x1000>;
|
||||
cpu = <&CPU2>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm2_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm3: etm@3f340000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f340000 0 0x1000>;
|
||||
cpu = <&CPU3>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm3_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm4: etm@3f440000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f440000 0 0x1000>;
|
||||
cpu = <&CPU4>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm5: etm@3f540000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f540000 0 0x1000>;
|
||||
cpu = <&CPU5>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm6: etm@3f640000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f640000 0 0x1000>;
|
||||
cpu = <&CPU6>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm7: etm@3f740000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x3f740000 0 0x1000>;
|
||||
cpu = <&CPU7>;
|
||||
clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>;
|
||||
clock-names = "apb_pclk", "clk_cs", "cs_src";
|
||||
|
||||
out-ports {
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&funnel_core_in_port7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
apb@70000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x70000000 0x10000000>;
|
||||
|
||||
uart0: serial@0 {
|
||||
compatible = "sprd,ums512-uart",
|
||||
"sprd,sc9836-uart";
|
||||
reg = <0x0 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@100000 {
|
||||
compatible = "sprd,ums512-uart",
|
||||
"sprd,sc9836-uart";
|
||||
reg = <0x100000 0x100>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio0: mmc@1100000 {
|
||||
compatible = "sprd,sdhci-r11";
|
||||
reg = <0x1100000 0x1000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "sdio", "enable";
|
||||
clocks = <&ap_clk CLK_SDIO0_2X>,
|
||||
<&apapb_gate CLK_SDIO0_EB>;
|
||||
assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
|
||||
assigned-clock-parents = <&pll1 CLK_RPLL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: mmc@1400000 {
|
||||
compatible = "sprd,sdhci-r11";
|
||||
reg = <0x1400000 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "sdio", "enable";
|
||||
clocks = <&ap_clk CLK_EMMC_2X>,
|
||||
<&apapb_gate CLK_EMMC_EB>;
|
||||
assigned-clocks = <&ap_clk CLK_EMMC_2X>;
|
||||
assigned-clock-parents = <&pll1 CLK_RPLL>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aon: bus@32000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x32000000 0x1000000>;
|
||||
|
||||
adi_bus: spi@100000 {
|
||||
compatible = "sprd,ums512-adi";
|
||||
reg = <0x100000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
|
||||
<17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
|
||||
<35 0x19b8>, <39 0x19ac>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ext_26m: clk-26m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "ext-26m";
|
||||
};
|
||||
|
||||
ext_32k: clk-32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "ext-32k";
|
||||
};
|
||||
|
||||
ext_4m: clk-4m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <4000000>;
|
||||
clock-output-names = "ext-4m";
|
||||
};
|
||||
|
||||
rco_100m: clk-100m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "rco-100m";
|
||||
};
|
||||
};
|
||||
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Reference in New Issue
Block a user