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Misc fixes:
- Fix a possible CPU hotplug deadlock bug caused by the new TSC synchronization code. - Fix a legacy PIC discovery bug that results in device troubles on affected systems, such as non-working keybards, etc. - Add a new Intel CPU model number to <asm/intel-family.h>. Signed-off-by: Ingo Molnar <mingo@kernel.org> -----BEGIN PGP SIGNATURE----- iQJFBAABCgAvFiEEBpT5eoXrXCwVQwEKEnMQ0APhK1gFAmU85uARHG1pbmdvQGtl cm5lbC5vcmcACgkQEnMQ0APhK1jSrhAAr3FrzkDWqLUUuDMWFEEVkTGz9GLc2uMP bGT7HApp301wGpFv35bbBVp7HKLSB9nFeLsWKQF6MBa2uSUiCxSBcSNfHVJ6jX1O Ac4hgl0Q/tZl0yZoag3u4j3FS57d9Qkzpg0QLTz9MVnQXEPTcDkli9tfSbRpxx3B WvcGwAD+VeMjeghIJHxTJW9KwouIf3gAzqoKE7TKEozJ4S2LbNs3nEsDGsRHJsPN jy/Fxlny6pdlkJArP/ILA9WO3yqBn2doIN9oqWKQCQtYbt1USnuJb5oCOXYAOijG A9iLJmMjDyN2TZ8lKYHBcHVmEVTeB+6VnikejcAaT4EMrArj5mdjL3K7McZ24NFh s8mx/S+v4mBExwNsaoq8kuUEZySWxNbFPLBjOq8BKIZYYDQUp1NK58CRWv9BAB6y GjgYlMYI6EGDb+QAoTKZ5KNqrwtUPuk2ijjJTB15DpgLkl7XmyoVOulrtVDrhuGZ Uuge9h0CLKnqD7lLfJdI7NLYxmZxPiQKbL9vrIqlk989UM5ItvttxWBNzhAdSTsG VIaXAOJgGDj74dJC+3b0umugKJcrycUFBy5/RxOg+OcnSPd5g/L4XWcLLk+OElE3 pFBetWmO2HU4pxhL1GdWsDuF+RkYug4XKQqQP2LJ8Zepff/jkF+hVJoLYUhQIF6A OMQv1N6/nSg= =k19e -----END PGP SIGNATURE----- Merge tag 'x86-urgent-2023-10-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull misc x86 fixes from Ingo Molnar: - Fix a possible CPU hotplug deadlock bug caused by the new TSC synchronization code - Fix a legacy PIC discovery bug that results in device troubles on affected systems, such as non-working keybards, etc - Add a new Intel CPU model number to <asm/intel-family.h> * tag 'x86-urgent-2023-10-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tsc: Defer marking TSC unstable to a worker x86/i8259: Skip probing when ACPI/MADT advertises PCAT compatibility x86/cpu: Add model number for Intel Arrow Lake mobile processor
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2af9b20dbb
@ -69,6 +69,8 @@ struct legacy_pic {
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void (*make_irq)(unsigned int irq);
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};
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void legacy_pic_pcat_compat(void);
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extern struct legacy_pic *legacy_pic;
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extern struct legacy_pic null_legacy_pic;
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@ -27,6 +27,7 @@
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* _X - regular server parts
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* _D - micro server parts
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* _N,_P - other mobile parts
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* _H - premium mobile parts
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* _S - other client parts
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*
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* Historical OPTDIFFs:
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@ -124,6 +125,7 @@
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#define INTEL_FAM6_METEORLAKE 0xAC
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#define INTEL_FAM6_METEORLAKE_L 0xAA
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#define INTEL_FAM6_ARROWLAKE_H 0xC5
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#define INTEL_FAM6_ARROWLAKE 0xC6
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#define INTEL_FAM6_LUNARLAKE_M 0xBD
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@ -148,6 +148,9 @@ static int __init acpi_parse_madt(struct acpi_table_header *table)
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pr_debug("Local APIC address 0x%08x\n", madt->address);
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}
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if (madt->flags & ACPI_MADT_PCAT_COMPAT)
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legacy_pic_pcat_compat();
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/* ACPI 6.3 and newer support the online capable bit. */
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if (acpi_gbl_FADT.header.revision > 6 ||
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(acpi_gbl_FADT.header.revision == 6 &&
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@ -32,6 +32,7 @@
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*/
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static void init_8259A(int auto_eoi);
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static bool pcat_compat __ro_after_init;
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static int i8259A_auto_eoi;
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DEFINE_RAW_SPINLOCK(i8259A_lock);
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@ -299,15 +300,32 @@ static void unmask_8259A(void)
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static int probe_8259A(void)
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{
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unsigned char new_val, probe_val = ~(1 << PIC_CASCADE_IR);
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unsigned long flags;
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unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
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unsigned char new_val;
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/*
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* Check to see if we have a PIC.
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* Mask all except the cascade and read
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* back the value we just wrote. If we don't
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* have a PIC, we will read 0xff as opposed to the
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* value we wrote.
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* If MADT has the PCAT_COMPAT flag set, then do not bother probing
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* for the PIC. Some BIOSes leave the PIC uninitialized and probing
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* fails.
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*
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* Right now this causes problems as quite some code depends on
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* nr_legacy_irqs() > 0 or has_legacy_pic() == true. This is silly
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* when the system has an IO/APIC because then PIC is not required
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* at all, except for really old machines where the timer interrupt
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* must be routed through the PIC. So just pretend that the PIC is
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* there and let legacy_pic->init() initialize it for nothing.
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*
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* Alternatively this could just try to initialize the PIC and
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* repeat the probe, but for cases where there is no PIC that's
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* just pointless.
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*/
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if (pcat_compat)
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return nr_legacy_irqs();
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/*
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* Check to see if we have a PIC. Mask all except the cascade and
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* read back the value we just wrote. If we don't have a PIC, we
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* will read 0xff as opposed to the value we wrote.
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*/
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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@ -429,5 +447,9 @@ static int __init i8259A_init_ops(void)
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return 0;
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}
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device_initcall(i8259A_init_ops);
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void __init legacy_pic_pcat_compat(void)
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{
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pcat_compat = true;
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}
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@ -15,6 +15,7 @@
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* ( The serial nature of the boot logic and the CPU hotplug lock
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* protects against more than 2 CPUs entering this code. )
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*/
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#include <linux/workqueue.h>
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#include <linux/topology.h>
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#include <linux/spinlock.h>
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#include <linux/kernel.h>
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@ -342,6 +343,13 @@ static inline unsigned int loop_timeout(int cpu)
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return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
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}
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static void tsc_sync_mark_tsc_unstable(struct work_struct *work)
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{
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mark_tsc_unstable("check_tsc_sync_source failed");
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}
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static DECLARE_WORK(tsc_sync_work, tsc_sync_mark_tsc_unstable);
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/*
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* The freshly booted CPU initiates this via an async SMP function call.
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*/
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@ -395,7 +403,7 @@ retry:
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"turning off TSC clock.\n", max_warp);
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if (random_warps)
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pr_warn("TSC warped randomly between CPUs\n");
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mark_tsc_unstable("check_tsc_sync_source failed");
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schedule_work(&tsc_sync_work);
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}
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/*
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