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ARM: dts: kirkwood: add pinctrl node to common SoC include

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All Kirkwood SoCs have their pinctrl registers at the same address.
Instead of replaying the same reg property on each SoC, have the
reg property set in the common SoC file already. This also allows
us to move common pinctrl settings to this node later on.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1398862602-29595-7-git-send-email-sebastian.hesselbarth@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Sebastian Hesselbarth 2014-04-30 14:56:33 +02:00 committed by Jason Cooper
parent a948396981
commit 2ab516adb3
5 changed files with 5 additions and 4 deletions
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1
arch/arm/boot/dts/kirkwood-6192.dtsi
View File

@ -37,7 +37,6 @@
ocp@f1000000 {
pinctrl: pin-controller@10000 {
compatible = "marvell,88f6192-pinctrl";
reg = <0x10000 0x20>;
pmx_nand: pmx-nand {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",

1
arch/arm/boot/dts/kirkwood-6281.dtsi
View File

@ -37,7 +37,6 @@
ocp@f1000000 {
pinctrl: pin-controller@10000 {
compatible = "marvell,88f6281-pinctrl";
reg = <0x10000 0x20>;
pmx_nand: pmx-nand {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",

1
arch/arm/boot/dts/kirkwood-6282.dtsi
View File

@ -58,7 +58,6 @@
pinctrl: pin-controller@10000 {
compatible = "marvell,88f6282-pinctrl";
reg = <0x10000 0x20>;
pmx_nand: pmx-nand {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",

1
arch/arm/boot/dts/kirkwood-98dx4122.dtsi
View File

@ -2,7 +2,6 @@
ocp@f1000000 {
pinctrl: pin-controller@10000 {
compatible = "marvell,98dx4122-pinctrl";
reg = <0x10000 0x20>;
pmx_nand: pmx-nand {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",

5
arch/arm/boot/dts/kirkwood.dtsi
View File

@ -71,6 +71,11 @@
#address-cells = <1>;
#size-cells = <1>;
pinctrl: pin-controller@10000 {
/* set compatible property in SoC file */
reg = <0x10000 0x20>;
};
core_clk: core-clocks@10030 {
compatible = "marvell,kirkwood-core-clock";
reg = <0x10030 0x4>;