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usb: renesas_usbhs: Fix DMAC sequence for receiving zero-length packet
The DREQE bit of the DnFIFOSEL should be set to 1 after the DE bit of
USB-DMAC on R-Car SoCs is set to 1 after the USB-DMAC received a
zero-length packet. Otherwise, a transfer completion interruption
of USB-DMAC doesn't happen. Even if the driver changes the sequence,
normal operations (transmit/receive without zero-length packet) will
not cause any side-effects. So, this patch fixes the sequence anyway.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[shimoda: revise the commit log]
Fixes: e73a9891b3
("usb: renesas_usbhs: add DMAEngine support")
Cc: <stable@vger.kernel.org> # v3.1+
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
parent
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@ -857,9 +857,9 @@ static void xfer_work(struct work_struct *work)
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fifo->name, usbhs_pipe_number(pipe), pkt->length, pkt->zero);
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usbhs_pipe_running(pipe, 1);
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usbhsf_dma_start(pipe, fifo);
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usbhs_pipe_set_trans_count_if_bulk(pipe, pkt->trans);
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dma_async_issue_pending(chan);
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usbhsf_dma_start(pipe, fifo);
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usbhs_pipe_enable(pipe);
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xfer_work_end:
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