Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-22 20:22:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

cxl/region: Fix x1 interleave to greater than x1 interleave routing

Browse Source 
In cases where the decode fans out as it traverses downstream, the
interleave granularity needs to increment to identify the port selector
bits out of the remaining address bits. For example, recall that with an
x2 parent port intereleave (IW == 1), the downstream decode for children
of those ports will either see address bit IG+8 always set, or address
bit IG+8 always clear. So if the child port needs to select a downstream
port it can only use address bits starting at IG+9 (where IG and IW are
the CXL encoded values for interleave granularity (ilog2(ig) - 8) and
ways (ilog2(iw))).

When the parent port interleave is x1 no such masking occurs and the
child port can maintain the granularity that was routed to the parent
port.

Reported-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Vishal Verma <vishal.l.verma@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/165973126583.1526540.657948655360009242.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams 2022-08-05 13:27:45 -07:00
parent 910bc55da8
commit 298d44d04b
1 changed files with 5 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/cxl/core/region.c
View File

@ -1025,7 +1025,11 @@ static int cxl_port_setup_targets(struct cxl_port *port,
return rc;
}
if (cxl_rr->nr_targets > 1) {
/*
* If @parent_port is masking address bits, pick the next unused address
* bit to route @port's targets.
*/
if (parent_iw > 1 && cxl_rr->nr_targets > 1) {
u32 address_bit = max(peig + peiw, eiw + peig);
eig = address_bit - eiw + 1;