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i5400_edac: convert driver to use the new edac ABI
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
d1afaa0a6e
commit
296da591ea
@ -18,6 +18,10 @@
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* Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
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* http://developer.intel.com/design/chipsets/datashts/313070.htm
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*
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* This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
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* 2 channels operating in lockstep no-mirror mode. Each channel can have up to
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* 4 dimm's, each with up to 8GB.
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*
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*/
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#include <linux/module.h>
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@ -44,12 +48,10 @@
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edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg)
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/* Limits for i5400 */
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#define NUM_MTRS_PER_BRANCH 4
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#define MAX_BRANCHES 2
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#define CHANNELS_PER_BRANCH 2
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#define MAX_DIMMS_PER_CHANNEL NUM_MTRS_PER_BRANCH
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#define MAX_CHANNELS 4
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/* max possible csrows per channel */
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#define MAX_CSROWS (MAX_DIMMS_PER_CHANNEL)
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#define DIMMS_PER_CHANNEL 4
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#define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH)
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/* Device 16,
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* Function 0: System Address
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@ -347,16 +349,16 @@ struct i5400_pvt {
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u16 mir0, mir1;
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u16 b0_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
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u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
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u16 b0_ambpresent0; /* Branch 0, Channel 0 */
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u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
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u16 b1_mtr[NUM_MTRS_PER_BRANCH]; /* Memory Technlogy Reg */
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u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */
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u16 b1_ambpresent0; /* Branch 1, Channel 8 */
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u16 b1_ambpresent1; /* Branch 1, Channel 1 */
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/* DIMM information matrix, allocating architecture maximums */
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struct i5400_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
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struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS];
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/* Actual values for this controller */
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int maxch; /* Max channels */
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@ -532,13 +534,15 @@ static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
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int ras, cas;
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int errnum;
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char *type = NULL;
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enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED;
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if (!allErrors)
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return; /* if no error, return now */
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if (allErrors & ERROR_FAT_MASK)
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if (allErrors & ERROR_FAT_MASK) {
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type = "FATAL";
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else if (allErrors & FERR_NF_UNCORRECTABLE)
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tp_event = HW_EVENT_ERR_FATAL;
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} else if (allErrors & FERR_NF_UNCORRECTABLE)
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type = "NON-FATAL uncorrected";
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else
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type = "NON-FATAL recoverable";
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@ -556,7 +560,7 @@ static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
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ras = nrec_ras(info);
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cas = nrec_cas(info);
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debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
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debugf0("\t\tDIMM= %d Channels= %d,%d (Branch= %d "
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"DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
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rank, channel, channel + 1, branch >> 1, bank,
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buf_id, rdwr_str(rdwr), ras, cas);
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@ -566,13 +570,13 @@ static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
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/* Form out message */
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snprintf(msg, sizeof(msg),
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"%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
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"RAS=%d CAS=%d %s Err=0x%lx (%s))",
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type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
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type, allErrors, error_name[errnum]);
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"Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)",
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bank, buf_id, ras, cas, allErrors, error_name[errnum]);
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/* Call the helper to output message */
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edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
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edac_mc_handle_error(tp_event, mci, 0, 0, 0,
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branch >> 1, -1, rank,
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rdwr ? "Write error" : "Read error",
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msg, NULL);
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}
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/*
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@ -630,7 +634,7 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
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/* Only 1 bit will be on */
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errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
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debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
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debugf0("\t\tDIMM= %d Channel= %d (Branch %d "
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"DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
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rank, channel, branch >> 1, bank,
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rdwr_str(rdwr), ras, cas);
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@ -642,8 +646,10 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
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branch >> 1, bank, rdwr_str(rdwr), ras, cas,
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allErrors, error_name[errnum]);
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/* Call the helper to output message */
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edac_mc_handle_fbd_ce(mci, rank, channel, msg);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
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branch >> 1, channel % 2, rank,
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rdwr ? "Write error" : "Read error",
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msg, NULL);
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return;
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}
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@ -831,8 +837,8 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
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/*
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* determine_amb_present
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*
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* the information is contained in NUM_MTRS_PER_BRANCH different
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* registers determining which of the NUM_MTRS_PER_BRANCH requires
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* the information is contained in DIMMS_PER_CHANNEL different
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* registers determining which of the DIMMS_PER_CHANNEL requires
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* knowing which channel is in question
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*
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* 2 branches, each with 2 channels
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@ -861,11 +867,11 @@ static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
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}
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/*
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* determine_mtr(pvt, csrow, channel)
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* determine_mtr(pvt, dimm, channel)
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*
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* return the proper MTR register as determine by the csrow and desired channel
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* return the proper MTR register as determine by the dimm and desired channel
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*/
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static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
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static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
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{
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int mtr;
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int n;
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@ -873,11 +879,11 @@ static int determine_mtr(struct i5400_pvt *pvt, int csrow, int channel)
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/* There is one MTR for each slot pair of FB-DIMMs,
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Each slot pair may be at branch 0 or branch 1.
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*/
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n = csrow;
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n = dimm;
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if (n >= NUM_MTRS_PER_BRANCH) {
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debugf0("ERROR: trying to access an invalid csrow: %d\n",
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csrow);
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if (n >= DIMMS_PER_CHANNEL) {
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debugf0("ERROR: trying to access an invalid dimm: %d\n",
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dimm);
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return 0;
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}
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@ -913,19 +919,19 @@ static void decode_mtr(int slot_row, u16 mtr)
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debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
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}
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static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
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static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
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struct i5400_dimm_info *dinfo)
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{
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int mtr;
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int amb_present_reg;
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int addrBits;
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mtr = determine_mtr(pvt, csrow, channel);
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mtr = determine_mtr(pvt, dimm, channel);
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if (MTR_DIMMS_PRESENT(mtr)) {
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amb_present_reg = determine_amb_present_reg(pvt, channel);
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/* Determine if there is a DIMM present in this DIMM slot */
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if (amb_present_reg & (1 << csrow)) {
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if (amb_present_reg & (1 << dimm)) {
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/* Start with the number of bits for a Bank
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* on the DRAM */
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addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
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@ -954,7 +960,7 @@ static void handle_channel(struct i5400_pvt *pvt, int csrow, int channel,
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static void calculate_dimm_size(struct i5400_pvt *pvt)
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{
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struct i5400_dimm_info *dinfo;
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int csrow, max_csrows;
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int dimm, max_dimms;
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char *p, *mem_buffer;
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int space, n;
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int channel;
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@ -968,32 +974,32 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
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return;
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}
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/* Scan all the actual CSROWS
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/* Scan all the actual DIMMS
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* and calculate the information for each DIMM
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* Start with the highest csrow first, to display it first
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* and work toward the 0th csrow
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* Start with the highest dimm first, to display it first
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* and work toward the 0th dimm
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*/
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max_csrows = pvt->maxdimmperch;
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for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
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max_dimms = pvt->maxdimmperch;
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for (dimm = max_dimms - 1; dimm >= 0; dimm--) {
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/* on an odd csrow, first output a 'boundary' marker,
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/* on an odd dimm, first output a 'boundary' marker,
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* then reset the message buffer */
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if (csrow & 0x1) {
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if (dimm & 0x1) {
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n = snprintf(p, space, "---------------------------"
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"--------------------------------");
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"-------------------------------");
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p += n;
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space -= n;
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debugf2("%s\n", mem_buffer);
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p = mem_buffer;
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space = PAGE_SIZE;
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}
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n = snprintf(p, space, "csrow %2d ", csrow);
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n = snprintf(p, space, "dimm %2d ", dimm);
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p += n;
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space -= n;
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for (channel = 0; channel < pvt->maxch; channel++) {
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dinfo = &pvt->dimm_info[csrow][channel];
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handle_channel(pvt, csrow, channel, dinfo);
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dinfo = &pvt->dimm_info[dimm][channel];
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handle_channel(pvt, dimm, channel, dinfo);
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n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
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p += n;
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space -= n;
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@ -1005,7 +1011,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
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/* Output the last bottom 'boundary' marker */
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n = snprintf(p, space, "---------------------------"
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"--------------------------------");
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"-------------------------------");
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p += n;
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space -= n;
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debugf2("%s\n", mem_buffer);
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@ -1013,7 +1019,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
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space = PAGE_SIZE;
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/* now output the 'channel' labels */
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n = snprintf(p, space, " ");
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n = snprintf(p, space, " ");
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p += n;
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space -= n;
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for (channel = 0; channel < pvt->maxch; channel++) {
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@ -1080,7 +1086,7 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
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debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
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/* Get the set of MTR[0-3] regs by each branch */
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for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++) {
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for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {
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int where = MTR0 + (slot_row * sizeof(u16));
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/* Branch 0 set of MTR registers */
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@ -1105,7 +1111,7 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
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/* Read and dump branch 0's MTRs */
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debugf2("\nMemory Technology Registers:\n");
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debugf2(" Branch 0:\n");
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for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++)
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for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
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decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
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pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
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@ -1122,7 +1128,7 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
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} else {
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/* Read and dump branch 1's MTRs */
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debugf2(" Branch 1:\n");
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for (slot_row = 0; slot_row < NUM_MTRS_PER_BRANCH; slot_row++)
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for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
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decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
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pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
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@ -1141,7 +1147,7 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
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}
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/*
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* i5400_init_csrows Initialize the 'csrows' table within
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* i5400_init_dimms Initialize the 'dimms' table within
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* the mci control structure with the
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* addressing of memory.
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*
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@ -1149,50 +1155,68 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
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* 0 success
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* 1 no actual memory found on this MC
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*/
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static int i5400_init_csrows(struct mem_ctl_info *mci)
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static int i5400_init_dimms(struct mem_ctl_info *mci)
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{
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struct i5400_pvt *pvt;
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struct csrow_info *p_csrow;
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int empty, channel_count;
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int max_csrows;
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struct dimm_info *dimm;
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int ndimms, channel_count;
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int max_dimms;
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int mtr;
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int size_mb;
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int channel;
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int csrow;
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struct dimm_info *dimm;
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int channel, slot;
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pvt = mci->pvt_info;
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channel_count = pvt->maxch;
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max_csrows = pvt->maxdimmperch;
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max_dimms = pvt->maxdimmperch;
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empty = 1; /* Assume NO memory */
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ndimms = 0;
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for (csrow = 0; csrow < max_csrows; csrow++) {
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p_csrow = &mci->csrows[csrow];
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/*
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* FIXME: remove pvt->dimm_info[slot][channel] and use the 3
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* layers here.
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*/
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for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size;
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channel++) {
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for (slot = 0; slot < mci->layers[2].size; slot++) {
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mtr = determine_mtr(pvt, slot, channel);
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/* use branch 0 for the basis */
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mtr = determine_mtr(pvt, csrow, 0);
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/* if no DIMMS on this slot, continue */
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if (!MTR_DIMMS_PRESENT(mtr))
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continue;
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/* if no DIMMS on this row, continue */
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if (!MTR_DIMMS_PRESENT(mtr))
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continue;
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dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
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channel / 2, channel % 2, slot);
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for (channel = 0; channel < pvt->maxch; channel++) {
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size_mb = pvt->dimm_info[csrow][channel].megabytes;
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size_mb = pvt->dimm_info[slot][channel].megabytes;
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debugf2("%s: dimm%zd (branch %d channel %d slot %d): %d.%03d GB\n",
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__func__, dimm - mci->dimms,
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channel / 2, channel % 2, slot,
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size_mb / 1000, size_mb % 1000);
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dimm = p_csrow->channels[channel].dimm;
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dimm->nr_pages = size_mb << 8;
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dimm->grain = 8;
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dimm->dtype = MTR_DRAM_WIDTH(mtr) ? DEV_X8 : DEV_X4;
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dimm->mtype = MEM_RDDR2;
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dimm->edac_mode = EDAC_SECDED;
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dimm->mtype = MEM_FB_DDR2;
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/*
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* The eccc mechanism is SDDC (aka SECC), with
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* is similar to Chipkill.
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*/
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dimm->edac_mode = MTR_DRAM_WIDTH(mtr) ?
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EDAC_S8ECD8ED : EDAC_S4ECD4ED;
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ndimms++;
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}
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empty = 0;
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}
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return empty;
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/*
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* When just one memory is provided, it should be at location (0,0,0).
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* With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+.
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*/
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if (ndimms == 1)
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mci->dimms[0].edac_mode = EDAC_SECDED;
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return (ndimms == 0);
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}
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/*
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@ -1228,9 +1252,7 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
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{
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struct mem_ctl_info *mci;
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struct i5400_pvt *pvt;
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int num_channels;
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int num_dimms_per_channel;
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int num_csrows;
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struct edac_mc_layer layers[3];
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if (dev_idx >= ARRAY_SIZE(i5400_devs))
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return -EINVAL;
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@ -1244,22 +1266,21 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
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if (PCI_FUNC(pdev->devfn) != 0)
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return -ENODEV;
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/* As we don't have a motherboard identification routine to determine
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* actual number of slots/dimms per channel, we thus utilize the
|
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* resource as specified by the chipset. Thus, we might have
|
||||
* have more DIMMs per channel than actually on the mobo, but this
|
||||
* allows the driver to support up to the chipset max, without
|
||||
* some fancy mobo determination.
|
||||
/*
|
||||
* allocate a new MC control structure
|
||||
*
|
||||
* This drivers uses the DIMM slot as "csrow" and the rest as "channel".
|
||||
*/
|
||||
num_dimms_per_channel = MAX_DIMMS_PER_CHANNEL;
|
||||
num_channels = MAX_CHANNELS;
|
||||
num_csrows = num_dimms_per_channel;
|
||||
|
||||
debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
|
||||
__func__, num_channels, num_dimms_per_channel, num_csrows);
|
||||
|
||||
/* allocate a new MC control structure */
|
||||
mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
|
||||
layers[0].type = EDAC_MC_LAYER_BRANCH;
|
||||
layers[0].size = MAX_BRANCHES;
|
||||
layers[0].is_virt_csrow = false;
|
||||
layers[1].type = EDAC_MC_LAYER_CHANNEL;
|
||||
layers[1].size = CHANNELS_PER_BRANCH;
|
||||
layers[1].is_virt_csrow = false;
|
||||
layers[2].type = EDAC_MC_LAYER_SLOT;
|
||||
layers[2].size = DIMMS_PER_CHANNEL;
|
||||
layers[2].is_virt_csrow = true;
|
||||
mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
|
||||
|
||||
if (mci == NULL)
|
||||
return -ENOMEM;
|
||||
@ -1270,8 +1291,8 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
|
||||
|
||||
pvt = mci->pvt_info;
|
||||
pvt->system_address = pdev; /* Record this device in our private */
|
||||
pvt->maxch = num_channels;
|
||||
pvt->maxdimmperch = num_dimms_per_channel;
|
||||
pvt->maxch = MAX_CHANNELS;
|
||||
pvt->maxdimmperch = DIMMS_PER_CHANNEL;
|
||||
|
||||
/* 'get' the pci devices we want to reserve for our use */
|
||||
if (i5400_get_devices(mci, dev_idx))
|
||||
@ -1293,13 +1314,13 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
|
||||
/* Set the function pointer to an actual operation function */
|
||||
mci->edac_check = i5400_check_error;
|
||||
|
||||
/* initialize the MC control structure 'csrows' table
|
||||
/* initialize the MC control structure 'dimms' table
|
||||
* with the mapping and control information */
|
||||
if (i5400_init_csrows(mci)) {
|
||||
if (i5400_init_dimms(mci)) {
|
||||
debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
|
||||
" because i5400_init_csrows() returned nonzero "
|
||||
" because i5400_init_dimms() returned nonzero "
|
||||
"value\n");
|
||||
mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
|
||||
mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */
|
||||
} else {
|
||||
debugf1("MC: Enable error reporting now\n");
|
||||
i5400_enable_error_reporting(mci);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user