mirror of
https://github.com/torvalds/linux.git
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Merge tag 'v4.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Pull "Rockchip dts64 changes for 4.9" from Heiko Stübner: 64bit Rockchip devicetree changes containing support for the recently added firmware reboot-flag support, one new board the Tronsmart Orion based on the rk3368 and a large number of newly supported peripherals for the rk3399 (type-c phy, usb2 phy, pcie controller and pcie phy, gmac, arm-pmu using ppi partitioning, efuse, saradc) as well as some smaller housekeeping and non-critical fixes. * tag 'v4.9-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (22 commits) arm64: dts: rockchip: add Type-C phy for RK3399 arm64: dts: rockchip: enable the gmac for rk3399 evb board arm64: dts: rockchip: add the gmac needed node for rk3399 arm64: dts: rockchip: support the pmu node for rk3399 arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs arm64: dts: rockchip: add the tcpc for rk3399 power domain arm64: dts: rockchip: add efuse0 device node for rk3399 arm64: dts: rockchip: configure PCIe support for rk3399-evb arm64: dts: rockchip: add the PCIe controller support for RK3399 arm64: dts: rockchip: add the PCIe PHY for RK3399 arm64: dts: rockchip: add the gmac power domain on rk3399 arm64: dts: rockchip: Add pinctrl entry for 32k clock on rk3399 arm64: dts: rockchip: set to CCI clock of RK3399 to 600M arm64: dts: rockchip: fix the address map for WDT0 and WDT1 arm64: dts: rockchip: add the saradc for rk3399 arm64: dts: rockchip: configure usb2-phy support for rk3399-evb arm64: dts: rockchip: add usb2-phy support for rk3399 arm64: dts: rockchip: add syscon-reboot-mode DT node soc: rockchip: add reboot-mode header arm64: dts: rockchip: remove broken-cd from sdio0 ...
This commit is contained in:
Arnd Bergmann
commit
291e287b97
@ -113,3 +113,7 @@ Rockchip platforms device tree bindings
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||||
- Rockchip RK3399 evb:
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Required root node properties:
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- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
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- Tronsmart Orion R68 Meta
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Required root node properties:
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- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
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@ -1,5 +1,6 @@
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
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382
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
Normal file
382
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
Normal file
@ -0,0 +1,382 @@
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/*
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* Copyright (c) 2016 Matthias Brugger <mbrugger@suse.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
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||||
*
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||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
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||||
*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "rk3368.dtsi"
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/ {
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model = "Rockchip Orion R68";
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compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
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chosen {
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stdout-path = "serial2:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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pinctrl-0 = <&emmc_reset>;
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pinctrl-names = "default";
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reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
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};
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ext_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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clock-output-names = "ext_gmac";
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};
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keys: gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_key>;
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power {
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wakeup-source;
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gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
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label = "GPIO Power";
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linux,code = <KEY_POWER>;
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};
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};
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leds: gpio-leds {
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compatible = "gpio-leds";
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red {
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gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
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label = "orion:red:led";
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pinctrl-names = "default";
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pinctrl-0 = <&led_ctl>;
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default-state = "on";
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};
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blue {
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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label = "orion:blue:led";
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pinctrl-names = "default";
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pinctrl-0 = <&stby_pwren>;
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default-state = "off";
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};
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};
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vcc_18: vcc18-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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/* supplies both host and otg */
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vcc_host: vcc-host-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&host_vbus_drv>;
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regulator-name = "vcc_host";
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||||
regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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vcc_io: vcc-io-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_io";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_sys>;
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};
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vcc_lan: vcc-lan-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_lan";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_io>;
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};
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||||
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||||
vcc_sd: vcc-sd-regulator {
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||||
compatible = "regulator-fixed";
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||||
regulator-name = "vcc_sd";
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||||
gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
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||||
regulator-min-microvolt = <1800000>;
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||||
regulator-max-microvolt = <3300000>;
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||||
regulator-always-on;
|
||||
regulator-boot-on;
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vin-supply = <&vcc_io>;
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};
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||||
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vcc_sys: vcc-sys-regulator {
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||||
compatible = "regulator-fixed";
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regulator-name = "vcc_sys";
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regulator-min-microvolt = <5000000>;
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||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vccio_sd: vcc-io-sd-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name= "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
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||||
regulator-always-on;
|
||||
regulator-boot-on;
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||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
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||||
vccio_wl: vccio-wl-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vccio_wl";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_io>;
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};
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||||
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||||
vdd_10: vdd-10-regulator {
|
||||
compatible = "regulator-fixed";
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||||
regulator-name = "vdd_10";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
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disable-wp;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&emmc_pwrseq>;
|
||||
mmc-hs200-1_2v;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
num-slots = <1>;
|
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
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status = "okay";
|
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};
|
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|
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&gmac {
|
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assigned-clocks = <&cru SCLK_MAC>;
|
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assigned-clock-parents = <&ext_gmac>;
|
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clock_in_out = "input";
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
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snps,reset-gpio = <&gpio3 12 0>;
|
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snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "ok";
|
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};
|
||||
|
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&i2c0 {
|
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status = "okay";
|
||||
|
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vdd_cpu: syr827@40 {
|
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compatible = "silergy,syr827";
|
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reg = <0x40>;
|
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fcs,suspend-voltage-selector = <1>;
|
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regulator-name = "vdd_cpu";
|
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regulator-enable-ramp-delay = <300>;
|
||||
regulator-min-microvolt = <712500>;
|
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regulator-max-microvolt = <1500000>;
|
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regulator-ramp-delay = <8000>;
|
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regulator-always-on;
|
||||
regulator-boot-on;
|
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vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
/* rtc_int is not connected */
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
||||
bias-disable;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
||||
bias-pull-up;
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc-clk {
|
||||
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc-cmd {
|
||||
rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
emmc_reset: emmc-reset {
|
||||
rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
pwr_key: pwr-key {
|
||||
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
stby_pwren: stby-pwren {
|
||||
rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_ctl: led-ctl {
|
||||
rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmmc-cd {
|
||||
rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus1: sdmmc-bus1 {
|
||||
rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<2 6 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<2 7 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
|
||||
<2 8 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
host_vbus_drv: host-vbus-drv {
|
||||
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_18>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
clock-frequency = <50000000>;
|
||||
clock-freq-min-max = <400000 50000000>;
|
||||
cap-sd-highspeed;
|
||||
card-detect-delay = <200>;
|
||||
keep-power-in-suspend;
|
||||
num-slots = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
@ -248,7 +248,6 @@
|
||||
&sdio0 {
|
||||
assigned-clocks = <&cru SCLK_SDIO0>;
|
||||
assigned-clock-parents = <&cru PLL_CPLL>;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
|
||||
@ -45,6 +45,7 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
@ -639,6 +640,15 @@
|
||||
compatible = "rockchip,rk3368-pmu-io-voltage-domain";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reboot-mode {
|
||||
compatible = "syscon-reboot-mode";
|
||||
offset = <0x200>;
|
||||
mode-normal = <BOOT_NORMAL>;
|
||||
mode-recovery = <BOOT_RECOVERY>;
|
||||
mode-bootloader = <BOOT_FASTBOOT>;
|
||||
mode-loader = <BOOT_BL_DOWNLOAD>;
|
||||
};
|
||||
};
|
||||
|
||||
cru: clock-controller@ff760000 {
|
||||
|
||||
@ -49,6 +49,13 @@
|
||||
compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
|
||||
"google,rk3399evb-rev2";
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
vdd_center: vdd-center {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm3 0 25000 0>;
|
||||
@ -69,18 +76,61 @@
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_phy: vcc-phy-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_phy";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_phy: vcc-phy-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_phy";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_phy>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -101,6 +151,36 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
num-lanes = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqn>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -133,4 +213,11 @@
|
||||
<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins =
|
||||
<4 25 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -45,6 +45,7 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/power/rk3399-power.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
@ -152,6 +153,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
pmu_a53 {
|
||||
compatible = "arm,cortex-a53-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
|
||||
};
|
||||
|
||||
pmu_a72 {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
@ -159,10 +170,10 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
|
||||
};
|
||||
|
||||
xin24m: xin24m {
|
||||
@ -181,8 +192,8 @@
|
||||
dmac_bus: dma-controller@ff6d0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xff6d0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&cru ACLK_DMAC0_PERILP>;
|
||||
clock-names = "apb_pclk";
|
||||
@ -191,19 +202,39 @@
|
||||
dmac_peri: dma-controller@ff6e0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xff6e0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&cru ACLK_DMAC1_PERILP>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
gmac: ethernet@fe300000 {
|
||||
compatible = "rockchip,rk3399-gmac";
|
||||
reg = <0x0 0xfe300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
|
||||
<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
|
||||
<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
|
||||
<&cru PCLK_GMAC>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_ref",
|
||||
"clk_mac_refout", "aclk_mac",
|
||||
"pclk_mac";
|
||||
power-domains = <&power RK3399_PD_GMAC>;
|
||||
resets = <&cru SRST_A_GMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio0: dwmmc@fe310000 {
|
||||
compatible = "rockchip,rk3399-dw-mshc",
|
||||
"rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe310000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
||||
@ -216,7 +247,7 @@
|
||||
compatible = "rockchip,rk3399-dw-mshc",
|
||||
"rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe320000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clock-freq-min-max = <400000 150000000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
||||
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
||||
@ -228,7 +259,7 @@
|
||||
sdhci: sdhci@fe330000 {
|
||||
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
|
||||
reg = <0x0 0xfe330000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
arasan,soc-ctl-syscon = <&grf>;
|
||||
assigned-clocks = <&cru SCLK_EMMC>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
@ -241,19 +272,60 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0: pcie@f8000000 {
|
||||
compatible = "rockchip,rk3399-pcie";
|
||||
reg = <0x0 0xf8000000 0x0 0x2000000>,
|
||||
<0x0 0xfd000000 0x0 0x1000000>;
|
||||
reg-names = "axi-base", "apb-base";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
bus-range = <0x0 0x1>;
|
||||
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
|
||||
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
|
||||
clock-names = "aclk", "aclk-perf",
|
||||
"hclk", "pm";
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "legacy", "client";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
|
||||
<0 0 0 2 &pcie0_intc 1>,
|
||||
<0 0 0 3 &pcie0_intc 2>,
|
||||
<0 0 0 4 &pcie0_intc 3>;
|
||||
msi-map = <0x0 &its 0x0 0x1000>;
|
||||
phys = <&pcie_phy>;
|
||||
phy-names = "pcie-phy";
|
||||
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
|
||||
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
|
||||
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
|
||||
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
|
||||
reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
|
||||
status = "disabled";
|
||||
|
||||
pcie0_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fe380000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xfe380000 0x0 0x20000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
|
||||
clock-names = "hclk_host0", "hclk_host0_arb";
|
||||
phys = <&u2phy0_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ohci: usb@fe3a0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xfe3a0000 0x0 0x20000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
|
||||
clock-names = "hclk_host0", "hclk_host0_arb";
|
||||
status = "disabled";
|
||||
@ -262,16 +334,18 @@
|
||||
usb_host1_ehci: usb@fe3c0000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xfe3c0000 0x0 0x20000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
|
||||
clock-names = "hclk_host1", "hclk_host1_arb";
|
||||
phys = <&u2phy1_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ohci: usb@fe3e0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xfe3e0000 0x0 0x20000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
|
||||
clock-names = "hclk_host1", "hclk_host1_arb";
|
||||
status = "disabled";
|
||||
@ -279,7 +353,7 @@
|
||||
|
||||
gic: interrupt-controller@fee00000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#interrupt-cells = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
@ -290,12 +364,34 @@
|
||||
<0x0 0xfff00000 0 0x10000>, /* GICC */
|
||||
<0x0 0xfff10000 0 0x10000>, /* GICH */
|
||||
<0x0 0xfff20000 0 0x10000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
its: interrupt-controller@fee20000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x0 0xfee20000 0x0 0x20000>;
|
||||
};
|
||||
|
||||
ppi-partitions {
|
||||
ppi_cluster0: interrupt-partition-0 {
|
||||
affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
|
||||
};
|
||||
|
||||
ppi_cluster1: interrupt-partition-1 {
|
||||
affinity = <&cpu_b0 &cpu_b1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
saradc: saradc@ff100000 {
|
||||
compatible = "rockchip,rk3399-saradc";
|
||||
reg = <0x0 0xff100000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#io-channel-cells = <1>;
|
||||
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
||||
clock-names = "saradc", "apb_pclk";
|
||||
resets = <&cru SRST_P_SARADC>;
|
||||
reset-names = "saradc-apb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@ff110000 {
|
||||
@ -305,7 +401,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -320,7 +416,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -335,7 +431,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -350,7 +446,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -365,7 +461,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c6_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -380,7 +476,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -393,7 +489,7 @@
|
||||
reg = <0x0 0xff180000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
@ -406,7 +502,7 @@
|
||||
reg = <0x0 0xff190000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
@ -419,7 +515,7 @@
|
||||
reg = <0x0 0xff1a0000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
@ -432,7 +528,7 @@
|
||||
reg = <0x0 0xff1b0000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
@ -445,7 +541,7 @@
|
||||
reg = <0x0 0xff1c0000 0x0 0x1000>;
|
||||
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
||||
#address-cells = <1>;
|
||||
@ -458,7 +554,7 @@
|
||||
reg = <0x0 0xff1d0000 0x0 0x1000>;
|
||||
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
||||
#address-cells = <1>;
|
||||
@ -471,7 +567,7 @@
|
||||
reg = <0x0 0xff1e0000 0x0 0x1000>;
|
||||
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
|
||||
#address-cells = <1>;
|
||||
@ -484,7 +580,7 @@
|
||||
reg = <0x0 0xff1f0000 0x0 0x1000>;
|
||||
clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
|
||||
#address-cells = <1>;
|
||||
@ -497,7 +593,7 @@
|
||||
reg = <0x0 0xff200000 0x0 0x1000>;
|
||||
clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
|
||||
#address-cells = <1>;
|
||||
@ -577,7 +673,7 @@
|
||||
tsadc: tsadc@ff260000 {
|
||||
compatible = "rockchip,rk3399-tsadc";
|
||||
reg = <0x0 0xff260000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
assigned-clocks = <&cru SCLK_TSADC>;
|
||||
assigned-clock-rates = <750000>;
|
||||
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
@ -594,6 +690,203 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qos_gmac: qos@ffa5c000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffa5c000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_hdcp: qos@ffa90000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffa90000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_iep: qos@ffa98000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffa98000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp0_m0: qos@ffaa0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffaa0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp0_m1: qos@ffaa0080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffaa0080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp1_m0: qos@ffaa8000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffaa8000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_isp1_m1: qos@ffaa8080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffaa8080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_rga_r: qos@ffab0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffab0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_rga_w: qos@ffab0080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffab0080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_video_m0: qos@ffab8000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffab8000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_video_m1_r: qos@ffac0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffac0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_video_m1_w: qos@ffac0080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffac0080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_vop_big_r: qos@ffac8000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffac8000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_vop_big_w: qos@ffac8080 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffac8080 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_vop_little: qos@ffad0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffad0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
qos_gpu: qos@ffae0000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x0 0xffae0000 0x0 0x20>;
|
||||
};
|
||||
|
||||
pmu: power-management@ff310000 {
|
||||
compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff310000 0x0 0x1000>;
|
||||
|
||||
/*
|
||||
* Note: RK3399 supports 6 voltage domains including VD_CORE_L,
|
||||
* VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
|
||||
* Some of the power domains are grouped together for every
|
||||
* voltage domain.
|
||||
* The detail contents as below.
|
||||
*/
|
||||
power: power-controller {
|
||||
compatible = "rockchip,rk3399-power-controller";
|
||||
#power-domain-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* These power domains are grouped by VD_CENTER */
|
||||
pd_iep@RK3399_PD_IEP {
|
||||
reg = <RK3399_PD_IEP>;
|
||||
clocks = <&cru ACLK_IEP>,
|
||||
<&cru HCLK_IEP>;
|
||||
pm_qos = <&qos_iep>;
|
||||
};
|
||||
pd_rga@RK3399_PD_RGA {
|
||||
reg = <RK3399_PD_RGA>;
|
||||
clocks = <&cru ACLK_RGA>,
|
||||
<&cru HCLK_RGA>;
|
||||
pm_qos = <&qos_rga_r>,
|
||||
<&qos_rga_w>;
|
||||
};
|
||||
pd_vcodec@RK3399_PD_VCODEC {
|
||||
reg = <RK3399_PD_VCODEC>;
|
||||
clocks = <&cru ACLK_VCODEC>,
|
||||
<&cru HCLK_VCODEC>;
|
||||
pm_qos = <&qos_video_m0>;
|
||||
};
|
||||
pd_vdu@RK3399_PD_VDU {
|
||||
reg = <RK3399_PD_VDU>;
|
||||
clocks = <&cru ACLK_VDU>,
|
||||
<&cru HCLK_VDU>;
|
||||
pm_qos = <&qos_video_m1_r>,
|
||||
<&qos_video_m1_w>;
|
||||
};
|
||||
|
||||
/* These power domains are grouped by VD_GPU */
|
||||
pd_gpu@RK3399_PD_GPU {
|
||||
reg = <RK3399_PD_GPU>;
|
||||
clocks = <&cru ACLK_GPU>;
|
||||
pm_qos = <&qos_gpu>;
|
||||
};
|
||||
|
||||
/* These power domains are grouped by VD_LOGIC */
|
||||
pd_gmac@RK3399_PD_GMAC {
|
||||
reg = <RK3399_PD_GMAC>;
|
||||
clocks = <&cru ACLK_GMAC>;
|
||||
pm_qos = <&qos_gmac>;
|
||||
};
|
||||
pd_vio@RK3399_PD_VIO {
|
||||
reg = <RK3399_PD_VIO>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pd_hdcp@RK3399_PD_HDCP {
|
||||
reg = <RK3399_PD_HDCP>;
|
||||
clocks = <&cru ACLK_HDCP>,
|
||||
<&cru HCLK_HDCP>,
|
||||
<&cru PCLK_HDCP>;
|
||||
pm_qos = <&qos_hdcp>;
|
||||
};
|
||||
pd_isp0@RK3399_PD_ISP0 {
|
||||
reg = <RK3399_PD_ISP0>;
|
||||
clocks = <&cru ACLK_ISP0>,
|
||||
<&cru HCLK_ISP0>;
|
||||
pm_qos = <&qos_isp0_m0>,
|
||||
<&qos_isp0_m1>;
|
||||
};
|
||||
pd_isp1@RK3399_PD_ISP1 {
|
||||
reg = <RK3399_PD_ISP1>;
|
||||
clocks = <&cru ACLK_ISP1>,
|
||||
<&cru HCLK_ISP1>;
|
||||
pm_qos = <&qos_isp1_m0>,
|
||||
<&qos_isp1_m1>;
|
||||
};
|
||||
pd_tcpc0@RK3399_PD_TCPC0 {
|
||||
reg = <RK3399_PD_TCPD0>;
|
||||
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
|
||||
<&cru SCLK_UPHY0_TCPDPHY_REF>;
|
||||
};
|
||||
pd_tcpc1@RK3399_PD_TCPC1 {
|
||||
reg = <RK3399_PD_TCPD1>;
|
||||
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
|
||||
<&cru SCLK_UPHY1_TCPDPHY_REF>;
|
||||
};
|
||||
pd_vo@RK3399_PD_VO {
|
||||
reg = <RK3399_PD_VO>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pd_vopb@RK3399_PD_VOPB {
|
||||
reg = <RK3399_PD_VOPB>;
|
||||
clocks = <&cru ACLK_VOP0>,
|
||||
<&cru HCLK_VOP0>;
|
||||
pm_qos = <&qos_vop_big_r>,
|
||||
<&qos_vop_big_w>;
|
||||
};
|
||||
pd_vopl@RK3399_PD_VOPL {
|
||||
reg = <RK3399_PD_VOPL>;
|
||||
clocks = <&cru ACLK_VOP1>,
|
||||
<&cru HCLK_VOP1>;
|
||||
pm_qos = <&qos_vop_little>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmugrf: syscon@ff320000 {
|
||||
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff320000 0x0 0x1000>;
|
||||
@ -611,7 +904,7 @@
|
||||
reg = <0x0 0xff350000 0x0 0x1000>;
|
||||
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
|
||||
#address-cells = <1>;
|
||||
@ -624,7 +917,7 @@
|
||||
reg = <0x0 0xff370000 0x0 0x100>;
|
||||
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
@ -639,7 +932,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -654,7 +947,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -669,7 +962,7 @@
|
||||
assigned-clock-rates = <200000000>;
|
||||
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
|
||||
clock-names = "i2c", "pclk";
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c8_xfer>;
|
||||
#address-cells = <1>;
|
||||
@ -721,6 +1014,35 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
efuse0: efuse@ff690000 {
|
||||
compatible = "rockchip,rk3399-efuse";
|
||||
reg = <0x0 0xff690000 0x0 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cru PCLK_EFUSE1024NS>;
|
||||
clock-names = "pclk_efuse";
|
||||
|
||||
/* Data cells */
|
||||
cpub_leakage: cpu-leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
gpu_leakage: gpu-leakage@18 {
|
||||
reg = <0x18 0x1>;
|
||||
};
|
||||
center_leakage: center-leakage@19 {
|
||||
reg = <0x19 0x1>;
|
||||
};
|
||||
cpul_leakage: cpu-leakage@1a {
|
||||
reg = <0x1a 0x1>;
|
||||
};
|
||||
logic_leakage: logic-leakage@1b {
|
||||
reg = <0x1b 0x1>;
|
||||
};
|
||||
wafer_info: wafer-info@1c {
|
||||
reg = <0x1c 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0x0 0xff750000 0x0 0x1000>;
|
||||
@ -741,7 +1063,7 @@
|
||||
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
|
||||
<&cru PCLK_PERIHP>,
|
||||
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
|
||||
<&cru PCLK_PERILP0>,
|
||||
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
|
||||
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
|
||||
assigned-clock-rates =
|
||||
<594000000>, <800000000>,
|
||||
@ -749,7 +1071,7 @@
|
||||
<150000000>, <75000000>,
|
||||
<37500000>,
|
||||
<100000000>, <100000000>,
|
||||
<50000000>,
|
||||
<50000000>, <600000000>,
|
||||
<100000000>, <50000000>;
|
||||
};
|
||||
|
||||
@ -764,6 +1086,40 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
u2phy0: usb2-phy@e450 {
|
||||
compatible = "rockchip,rk3399-usb2phy";
|
||||
reg = <0xe450 0x10>;
|
||||
clocks = <&cru SCLK_USB2PHY0_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clk_usbphy0_480m";
|
||||
status = "disabled";
|
||||
|
||||
u2phy0_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "linestate";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
u2phy1: usb2-phy@e460 {
|
||||
compatible = "rockchip,rk3399-usb2phy";
|
||||
reg = <0xe460 0x10>;
|
||||
clocks = <&cru SCLK_USB2PHY1_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clk_usbphy1_480m";
|
||||
status = "disabled";
|
||||
|
||||
u2phy1_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "linestate";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
emmc_phy: phy@f780 {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
reg = <0xf780 0x24>;
|
||||
@ -772,19 +1128,85 @@
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie_phy: pcie-phy {
|
||||
compatible = "rockchip,rk3399-pcie-phy";
|
||||
clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
clock-names = "refclk";
|
||||
#phy-cells = <0>;
|
||||
resets = <&cru SRST_PCIEPHY>;
|
||||
reset-names = "phy";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@ff840000 {
|
||||
tcphy0: phy@ff7c0000 {
|
||||
compatible = "rockchip,rk3399-typec-phy";
|
||||
reg = <0x0 0xff7c0000 0x0 0x40000>;
|
||||
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
|
||||
<&cru SCLK_UPHY0_TCPDPHY_REF>;
|
||||
clock-names = "tcpdcore", "tcpdphy-ref";
|
||||
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
|
||||
assigned-clock-rates = <50000000>;
|
||||
resets = <&cru SRST_UPHY0>,
|
||||
<&cru SRST_UPHY0_PIPE_L00>,
|
||||
<&cru SRST_P_UPHY0_TCPHY>;
|
||||
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,typec-conn-dir = <0xe580 0 16>;
|
||||
rockchip,usb3tousb2-en = <0xe580 3 19>;
|
||||
rockchip,external-psm = <0xe588 14 30>;
|
||||
rockchip,pipe-status = <0xe5c0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
tcphy0_dp: dp-port {
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
tcphy0_usb3: usb3-port {
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcphy1: phy@ff800000 {
|
||||
compatible = "rockchip,rk3399-typec-phy";
|
||||
reg = <0x0 0xff800000 0x0 0x40000>;
|
||||
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
|
||||
<&cru SCLK_UPHY1_TCPDPHY_REF>;
|
||||
clock-names = "tcpdcore", "tcpdphy-ref";
|
||||
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
|
||||
assigned-clock-rates = <50000000>;
|
||||
resets = <&cru SRST_UPHY1>,
|
||||
<&cru SRST_UPHY1_PIPE_L00>,
|
||||
<&cru SRST_P_UPHY1_TCPHY>;
|
||||
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,typec-conn-dir = <0xe58c 0 16>;
|
||||
rockchip,usb3tousb2-en = <0xe58c 3 19>;
|
||||
rockchip,external-psm = <0xe594 14 30>;
|
||||
rockchip,pipe-status = <0xe5c0 16 16>;
|
||||
status = "disabled";
|
||||
|
||||
tcphy1_dp: dp-port {
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
tcphy1_usb3: usb3-port {
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog@ff848000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x0 0xff840000 0x0 0x100>;
|
||||
reg = <0x0 0xff848000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_WDT>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
};
|
||||
|
||||
rktimer: rktimer@ff850000 {
|
||||
compatible = "rockchip,rk3399-timer";
|
||||
reg = <0x0 0xff850000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
|
||||
clock-names = "pclk", "timer";
|
||||
};
|
||||
@ -792,7 +1214,7 @@
|
||||
spdif: spdif@ff870000 {
|
||||
compatible = "rockchip,rk3399-spdif";
|
||||
reg = <0x0 0xff870000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dmac_bus 7>;
|
||||
dma-names = "tx";
|
||||
clock-names = "mclk", "hclk";
|
||||
@ -806,7 +1228,7 @@
|
||||
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x0 0xff880000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
|
||||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
@ -819,7 +1241,7 @@
|
||||
i2s1: i2s@ff890000 {
|
||||
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x0 0xff890000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
|
||||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
@ -832,7 +1254,7 @@
|
||||
i2s2: i2s@ff8a0000 {
|
||||
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
|
||||
reg = <0x0 0xff8a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
|
||||
dma-names = "tx", "rx";
|
||||
clock-names = "i2s_clk", "i2s_hclk";
|
||||
@ -852,7 +1274,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff720000 0x0 0x100>;
|
||||
clocks = <&pmucru PCLK_GPIO0_PMU>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
@ -865,7 +1287,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff730000 0x0 0x100>;
|
||||
clocks = <&pmucru PCLK_GPIO1_PMU>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
@ -878,7 +1300,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff780000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
@ -891,7 +1313,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff788000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_GPIO3>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
@ -904,7 +1326,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xff790000 0x0 0x100>;
|
||||
clocks = <&cru PCLK_GPIO4>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
@ -955,6 +1377,72 @@
|
||||
drive-strength = <13>;
|
||||
};
|
||||
|
||||
clock {
|
||||
clk_32k: clk-32k {
|
||||
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
rgmii_pins: rgmii-pins {
|
||||
rockchip,pins =
|
||||
/* mac_txclk */
|
||||
<3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_rxclk */
|
||||
<3 14 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_mdio */
|
||||
<3 13 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_txen */
|
||||
<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_clk */
|
||||
<3 11 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxdv */
|
||||
<3 9 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_mdc */
|
||||
<3 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxd1 */
|
||||
<3 7 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxd0 */
|
||||
<3 6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_txd1 */
|
||||
<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_txd0 */
|
||||
<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_rxd3 */
|
||||
<3 3 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxd2 */
|
||||
<3 2 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_txd3 */
|
||||
<3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_txd2 */
|
||||
<3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
|
||||
};
|
||||
|
||||
rmii_pins: rmii-pins {
|
||||
rockchip,pins =
|
||||
/* mac_mdio */
|
||||
<3 13 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_txen */
|
||||
<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_clk */
|
||||
<3 11 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxer */
|
||||
<3 10 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxdv */
|
||||
<3 9 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_mdc */
|
||||
<3 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxd1 */
|
||||
<3 7 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_rxd0 */
|
||||
<3 6 RK_FUNC_1 &pcfg_pull_none>,
|
||||
/* mac_txd1 */
|
||||
<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
|
||||
/* mac_txd0 */
|
||||
<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
i2c0_xfer: i2c0-xfer {
|
||||
rockchip,pins =
|
||||
@ -1326,5 +1814,18 @@
|
||||
<1 14 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_clkreqn: pci-clkreqn {
|
||||
rockchip,pins =
|
||||
<2 26 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_clkreqnb: pci-clkreqnb {
|
||||
rockchip,pins =
|
||||
<4 24 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
15
include/dt-bindings/soc/rockchip,boot-mode.h
Normal file
15
include/dt-bindings/soc/rockchip,boot-mode.h
Normal file
@ -0,0 +1,15 @@
|
||||
#ifndef __ROCKCHIP_BOOT_MODE_H
|
||||
#define __ROCKCHIP_BOOT_MODE_H
|
||||
|
||||
/*high 24 bits is tag, low 8 bits is type*/
|
||||
#define REBOOT_FLAG 0x5242C300
|
||||
/* normal boot */
|
||||
#define BOOT_NORMAL (REBOOT_FLAG + 0)
|
||||
/* enter bootloader rockusb mode */
|
||||
#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1)
|
||||
/* enter recovery */
|
||||
#define BOOT_RECOVERY (REBOOT_FLAG + 3)
|
||||
/* enter fastboot mode */
|
||||
#define BOOT_FASTBOOT (REBOOT_FLAG + 9)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user