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igb: add support for the 82580 phy
This patch adds support for the phy included in the 82580 silicon family. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexander Duyck
David S. Miller
parent
164165dad7
commit
2909c3f79d
@ -93,6 +93,7 @@ enum e1000_phy_type {
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e1000_phy_gg82563,
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e1000_phy_igp_3,
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e1000_phy_ife,
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e1000_phy_82580,
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};
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enum e1000_bus_type {
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@ -420,6 +420,57 @@ out:
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return ret_val;
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}
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/**
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* igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
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* @hw: pointer to the HW structure
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*
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* Sets up Carrier-sense on Transmit and downshift values.
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**/
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s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u16 phy_data;
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if (phy->reset_disable) {
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ret_val = 0;
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goto out;
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}
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if (phy->type == e1000_phy_82580) {
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ret_val = hw->phy.ops.reset(hw);
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if (ret_val) {
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hw_dbg("Error resetting the PHY.\n");
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goto out;
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}
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}
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/* Enable CRS on TX. This must be set for half-duplex operation. */
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ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
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if (ret_val)
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goto out;
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phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
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/* Enable downshift */
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phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
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ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
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if (ret_val)
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goto out;
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/* Set number of link attempts before downshift */
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ret_val = phy->ops.read_reg(hw, I82580_CTRL_REG, &phy_data);
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if (ret_val)
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goto out;
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phy_data &= ~I82580_CTRL_DOWNSHIFT_MASK;
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ret_val = phy->ops.write_reg(hw, I82580_CTRL_REG, phy_data);
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out:
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return ret_val;
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}
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/**
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* igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
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* @hw: pointer to the HW structure
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@ -1888,3 +1939,194 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
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return 0;
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}
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/**
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* igb_check_polarity_82580 - Checks the polarity.
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* @hw: pointer to the HW structure
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*
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* Success returns 0, Failure returns -E1000_ERR_PHY (-2)
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*
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* Polarity is determined based on the PHY specific status register.
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**/
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s32 igb_check_polarity_82580(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u16 data;
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ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
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if (!ret_val)
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phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
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? e1000_rev_polarity_reversed
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: e1000_rev_polarity_normal;
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return ret_val;
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}
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/**
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* igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
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* @hw: pointer to the HW structure
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*
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* Calls the PHY setup function to force speed and duplex. Clears the
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* auto-crossover to force MDI manually. Waits for link and returns
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* successful if link up is successful, else -E1000_ERR_PHY (-2).
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**/
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s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u16 phy_data;
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bool link;
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ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
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if (ret_val)
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goto out;
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igb_phy_force_speed_duplex_setup(hw, &phy_data);
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ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
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if (ret_val)
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goto out;
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/*
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* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
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* forced whenever speed and duplex are forced.
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*/
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ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
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if (ret_val)
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goto out;
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phy_data &= ~I82580_PHY_CTRL2_AUTO_MDIX;
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phy_data &= ~I82580_PHY_CTRL2_FORCE_MDI_MDIX;
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ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
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if (ret_val)
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goto out;
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hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
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udelay(1);
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if (phy->autoneg_wait_to_complete) {
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hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
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ret_val = igb_phy_has_link(hw,
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PHY_FORCE_LIMIT,
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100000,
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&link);
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if (ret_val)
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goto out;
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if (!link)
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hw_dbg("Link taking longer than expected.\n");
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/* Try once more */
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ret_val = igb_phy_has_link(hw,
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PHY_FORCE_LIMIT,
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100000,
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&link);
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if (ret_val)
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goto out;
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}
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out:
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return ret_val;
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}
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/**
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* igb_get_phy_info_82580 - Retrieve I82580 PHY information
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* @hw: pointer to the HW structure
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*
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* Read PHY status to determine if link is up. If link is up, then
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* set/determine 10base-T extended distance and polarity correction. Read
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* PHY port status to determine MDI/MDIx and speed. Based on the speed,
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* determine on the cable length, local and remote receiver.
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**/
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s32 igb_get_phy_info_82580(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u16 data;
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bool link;
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ret_val = igb_phy_has_link(hw, 1, 0, &link);
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if (ret_val)
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goto out;
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if (!link) {
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hw_dbg("Phy info is only valid if link is up\n");
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ret_val = -E1000_ERR_CONFIG;
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goto out;
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}
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phy->polarity_correction = true;
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ret_val = igb_check_polarity_82580(hw);
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if (ret_val)
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goto out;
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ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
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if (ret_val)
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goto out;
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phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
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if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
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I82580_PHY_STATUS2_SPEED_1000MBPS) {
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ret_val = hw->phy.ops.get_cable_length(hw);
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if (ret_val)
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goto out;
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ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
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if (ret_val)
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goto out;
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phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
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? e1000_1000t_rx_status_ok
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: e1000_1000t_rx_status_not_ok;
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phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
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? e1000_1000t_rx_status_ok
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: e1000_1000t_rx_status_not_ok;
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} else {
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phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
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phy->local_rx = e1000_1000t_rx_status_undefined;
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phy->remote_rx = e1000_1000t_rx_status_undefined;
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}
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out:
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return ret_val;
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}
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/**
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* igb_get_cable_length_82580 - Determine cable length for 82580 PHY
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* @hw: pointer to the HW structure
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*
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* Reads the diagnostic status register and verifies result is valid before
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* placing it in the phy_cable_length field.
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**/
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s32 igb_get_cable_length_82580(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u16 phy_data, length;
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ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
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if (ret_val)
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goto out;
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length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
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I82580_DSTATUS_CABLE_LENGTH_SHIFT;
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if (length == E1000_CABLE_LENGTH_UNDEFINED)
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ret_val = -E1000_ERR_PHY;
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phy->cable_length = length;
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out:
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return ret_val;
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}
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@ -63,6 +63,11 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
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s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
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s32 igb_check_polarity_82580(struct e1000_hw *hw);
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s32 igb_get_phy_info_82580(struct e1000_hw *hw);
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s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
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s32 igb_get_cable_length_82580(struct e1000_hw *hw);
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/* IGP01E1000 Specific Registers */
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#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
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@ -77,6 +82,33 @@ s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
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#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
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#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
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#define I82580_ADDR_REG 16
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#define I82580_CFG_REG 22
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#define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15)
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#define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
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#define I82580_CTRL_REG 23
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#define I82580_CTRL_DOWNSHIFT_MASK (7 << 10)
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/* 82580 specific PHY registers */
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#define I82580_PHY_CTRL_2 18
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#define I82580_PHY_LBK_CTRL 19
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#define I82580_PHY_STATUS_2 26
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#define I82580_PHY_DIAG_STATUS 31
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/* I82580 PHY Status 2 */
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#define I82580_PHY_STATUS2_REV_POLARITY 0x0400
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#define I82580_PHY_STATUS2_MDIX 0x0800
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#define I82580_PHY_STATUS2_SPEED_MASK 0x0300
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#define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
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#define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100
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/* I82580 PHY Control 2 */
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#define I82580_PHY_CTRL2_AUTO_MDIX 0x0400
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#define I82580_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
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/* I82580 PHY Diagnostics Status */
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#define I82580_DSTATUS_CABLE_LENGTH 0x03FC
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#define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
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/* Enable flexible speed on link-up */
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#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
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#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
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