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media: i2c: mt9p031: Drop support for legacy platform data
No user of the mt9p031_platform_data legacy platform data for board files exist in the kernel anymore. Drop support from the driver. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Tarang Raval <tarang.raval@siliconsignals.io> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Laurent Pinchart
Hans Verkuil
parent
8e9a03bd41
commit
28aeaeaca6
@ -15839,7 +15839,6 @@ S: Maintained
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T: git git://linuxtv.org/media_tree.git
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F: Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml
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F: drivers/media/i2c/mt9p031.c
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F: include/media/i2c/mt9p031.h
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MT9T112 APTINA CAMERA SENSOR
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M: Jacopo Mondi <jacopo@jmondi.org>
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@ -24,7 +24,6 @@
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#include <linux/slab.h>
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#include <linux/videodev2.h>
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#include <media/i2c/mt9p031.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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@ -118,13 +117,16 @@ struct mt9p031 {
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struct media_pad pad;
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struct v4l2_rect crop; /* Sensor window */
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struct v4l2_mbus_framefmt format;
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struct mt9p031_platform_data *pdata;
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struct mutex power_lock; /* lock to protect power_count */
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int power_count;
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struct clk *clk;
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struct regulator_bulk_data regulators[3];
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unsigned int pixclk_pol:1;
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int ext_freq;
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int target_freq;
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u32 code;
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struct aptina_pll pll;
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unsigned int clk_div;
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@ -225,7 +227,6 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
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};
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struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev);
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struct mt9p031_platform_data *pdata = mt9p031->pdata;
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unsigned long ext_freq;
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int ret;
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@ -233,7 +234,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
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if (IS_ERR(mt9p031->clk))
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return PTR_ERR(mt9p031->clk);
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ret = clk_set_rate(mt9p031->clk, pdata->ext_freq);
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ret = clk_set_rate(mt9p031->clk, mt9p031->ext_freq);
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if (ret < 0)
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return ret;
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@ -245,7 +246,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
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if (ext_freq > limits.ext_clock_max) {
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unsigned int div;
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div = DIV_ROUND_UP(ext_freq, pdata->target_freq);
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div = DIV_ROUND_UP(ext_freq, mt9p031->target_freq);
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div = roundup_pow_of_two(div) / 2;
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mt9p031->clk_div = min_t(unsigned int, div, 64);
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@ -255,7 +256,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031)
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}
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mt9p031->pll.ext_clock = ext_freq;
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mt9p031->pll.pix_clock = pdata->target_freq;
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mt9p031->pll.pix_clock = mt9p031->target_freq;
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mt9p031->use_pll = true;
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return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll);
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@ -376,7 +377,7 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on)
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}
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/* Configure the pixel clock polarity */
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if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) {
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if (mt9p031->pixclk_pol) {
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ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL,
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MT9P031_PIXEL_CLOCK_INVERT);
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if (ret < 0)
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@ -1057,53 +1058,42 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = {
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* Driver initialization and probing
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*/
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static struct mt9p031_platform_data *
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mt9p031_get_pdata(struct i2c_client *client)
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static int mt9p031_parse_of(struct mt9p031 *mt9p031, struct device *dev)
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{
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struct mt9p031_platform_data *pdata = NULL;
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struct device_node *np;
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struct v4l2_fwnode_endpoint endpoint = {
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.bus_type = V4L2_MBUS_PARALLEL
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};
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int ret;
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if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
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return client->dev.platform_data;
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if (!dev->of_node)
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return -EINVAL;
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np = of_graph_get_endpoint_by_regs(client->dev.of_node, 0, -1);
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np = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
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if (!np)
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return NULL;
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return -EINVAL;
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if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
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goto done;
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pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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goto done;
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of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq);
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of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq);
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pdata->pixclk_pol = !!(endpoint.bus.parallel.flags &
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V4L2_MBUS_PCLK_SAMPLE_RISING);
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done:
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ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint);
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of_node_put(np);
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return pdata;
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if (ret)
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return ret;
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of_property_read_u32(np, "input-clock-frequency", &mt9p031->ext_freq);
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of_property_read_u32(np, "pixel-clock-frequency", &mt9p031->target_freq);
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mt9p031->pixclk_pol = !!(endpoint.bus.parallel.flags &
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V4L2_MBUS_PCLK_SAMPLE_RISING);
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return 0;
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}
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static int mt9p031_probe(struct i2c_client *client)
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{
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struct mt9p031_platform_data *pdata = mt9p031_get_pdata(client);
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struct i2c_adapter *adapter = client->adapter;
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struct mt9p031 *mt9p031;
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unsigned int i;
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int ret;
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if (pdata == NULL) {
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dev_err(&client->dev, "No platform data\n");
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return -EINVAL;
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}
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if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
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dev_warn(&client->dev,
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"I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
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@ -1114,7 +1104,12 @@ static int mt9p031_probe(struct i2c_client *client)
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if (mt9p031 == NULL)
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return -ENOMEM;
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mt9p031->pdata = pdata;
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ret = mt9p031_parse_of(mt9p031, &client->dev);
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if (ret) {
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dev_err(&client->dev, "Failed to parse DT properties\n");
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return ret;
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}
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mt9p031->output_control = MT9P031_OUTPUT_CONTROL_DEF;
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mt9p031->mode2 = MT9P031_READ_MODE_2_ROW_BLC;
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mt9p031->code = (uintptr_t)i2c_get_match_data(client);
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@ -1145,8 +1140,8 @@ static int mt9p031_probe(struct i2c_client *client)
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v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
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V4L2_CID_VFLIP, 0, 1, 1, 0);
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v4l2_ctrl_new_std(&mt9p031->ctrls, &mt9p031_ctrl_ops,
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V4L2_CID_PIXEL_RATE, pdata->target_freq,
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pdata->target_freq, 1, pdata->target_freq);
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V4L2_CID_PIXEL_RATE, mt9p031->target_freq,
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mt9p031->target_freq, 1, mt9p031->target_freq);
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v4l2_ctrl_new_std_menu_items(&mt9p031->ctrls, &mt9p031_ctrl_ops,
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V4L2_CID_TEST_PATTERN,
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ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0,
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@ -1,18 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef MT9P031_H
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#define MT9P031_H
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struct v4l2_subdev;
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/*
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* struct mt9p031_platform_data - MT9P031 platform data
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* @ext_freq: Input clock frequency
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* @target_freq: Pixel clock frequency
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*/
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struct mt9p031_platform_data {
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unsigned int pixclk_pol:1;
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int ext_freq;
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int target_freq;
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};
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#endif
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