From bc0c0c302925ff02fab06633ac2f732323b9e6f9 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:50 +0200 Subject: [PATCH 1/6] ARM: dts: pxa: add pxa framebuffer device Add the framebuffer device, or display controller, available on pxa2xx and pxa3xx platforms. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa2xx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index 5e5af078b9b5..3ff077ca4400 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -140,5 +140,13 @@ reg = <0x40900000 0x3c>; interrupts = <30 31>; }; + + lcd-controller@40500000 { + compatible = "marvell,pxa2xx-lcdc"; + reg = <0x44000000 0x10000>; + interrupts = <17>; + clocks = <&clks CLK_LCD>; + status = "disabled"; + }; }; }; From 85deaec8e900a98e0ab422620035803541965ef1 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:51 +0200 Subject: [PATCH 2/6] ARM: dts: pxa: add pxa3xx pwm nodes The pxa3xx SoC has 4 PWMs, exactly as the pxa27x does. Add them to the description. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index fec47bcd8292..5767ed4957ae 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -95,6 +95,38 @@ clocks = <&clks CLK_USBHOST>; status = "disabled"; }; + + pwm0: pwm@40b00000 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40b00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + status = "disabled"; + }; + + pwm1: pwm@40b00010 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40b00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + status = "disabled"; + }; + + pwm2: pwm@40c00000 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40c00000 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM0>; + status = "disabled"; + }; + + pwm3: pwm@40c00010 { + compatible = "marvell,pxa270-pwm"; + reg = <0x40c00010 0x10>; + #pwm-cells = <1>; + clocks = <&clks CLK_PWM1>; + status = "disabled"; + }; }; clocks { From ca91c703aeb192d98cacf733267e0e7c256cd7b6 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:52 +0200 Subject: [PATCH 3/6] ARM: dts: add pincontroller to pxa27x Add the new pincontrol driver to pxa27x based boards. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa27x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index 210192c38df3..9e73dc6b3ed3 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -22,8 +22,15 @@ marvell,intc-nr-irqs = <34>; }; + pinctrl: pinctrl@40e00000 { + reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 + 0x40f00020 0x10>; + compatible = "marvell,pxa27x-pinctrl"; + }; + gpio: gpio@40e00000 { compatible = "intel,pxa27x-gpio"; + gpio-ranges = <&pinctrl 0 0 128>; clocks = <&clks CLK_NONE>; }; From aa71cc501494cef368c439dbb90cd9dba74c8d8e Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:53 +0200 Subject: [PATCH 4/6] ARM: dts: pxa: fix the ohci clock for pxa3xx Fix the USB host clock, which is CLK_USBH. CLK_USBHOST is the clock of the usb host of pxa27x SoCs. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 5767ed4957ae..5e2dea0f1436 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -92,7 +92,7 @@ compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x10000>; interrupts = <3>; - clocks = <&clks CLK_USBHOST>; + clocks = <&clks CLK_USBH>; status = "disabled"; }; From 3a23249e5f92042e5431643acdb310849c38c8f6 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:54 +0200 Subject: [PATCH 5/6] ARM: dts: pxa: add pinctrl to pxa3xx Add pincontrol to pxa3xx, based on pinconf-simple. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 5e2dea0f1436..6995b11ce042 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -43,6 +43,15 @@ marvell,intc-nr-irqs = <56>; }; + pinctrl: pinctrl@40e10000 { + compatible = "pinconf-single"; + reg = <0x40e10000 0xffff>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7>; + }; + gpio: gpio@40e00000 { compatible = "intel,pxa3xx-gpio"; reg = <0x40e00000 0x10000>; From fca43c3f7e6fe421194e9b21eabc72604edac16c Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Tue, 5 Apr 2016 08:35:55 +0200 Subject: [PATCH 6/6] ARM: dts: pxa3xx: add pincontrol helpers The various pxa3xx variants have a really weird pin scheme assignement, when you want the pin number relative to a known gpio pin. This change adds the various tools to ease up writing the pinmux and pinconf devicetree parts. Signed-off-by: Robert Jarzmik --- arch/arm/boot/dts/pxa3xx.dtsi | 90 +++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 6995b11ce042..9d6f3aacedb7 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -1,6 +1,96 @@ /* The pxa3xx skeleton simply augments the 2xx version */ #include "pxa2xx.dtsi" +#define MFP_PIN_PXA300(gpio) \ + ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ + (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ + (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + 0) + +#define MFP_PIN_PXA310(gpio) \ + ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \ + (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \ + (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + (gpio <= 262) ? 0 : \ + (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \ + 0) + +#define MFP_PIN_PXA320(gpio) \ + ((gpio <= 4) ? (0x0124 + 4 * gpio) : \ + (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \ + (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) : \ + (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) : \ + (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) : \ + (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) : \ + (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) : \ + (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) : \ + (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \ + 0) + +/* + * MFP Alternate functions for pins having a gpio. + * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 > + */ +#define MFP_AF0 (0 << 0) +#define MFP_AF1 (1 << 0) +#define MFP_AF2 (2 << 0) +#define MFP_AF3 (3 << 0) +#define MFP_AF4 (4 << 0) +#define MFP_AF5 (5 << 0) +#define MFP_AF6 (6 << 0) + +/* + * MFP drive strength functions for pins. + * Example of use: pinctrl-single,drive-strength = MFP_DS03X; + */ +#define MFP_DSMSK (0x7 << 10) +#define MFP_DS01X < (0x0 << 10) MFP_DSMSK > +#define MFP_DS02X < (0x1 << 10) MFP_DSMSK > +#define MFP_DS03X < (0x2 << 10) MFP_DSMSK > +#define MFP_DS04X < (0x3 << 10) MFP_DSMSK > +#define MFP_DS06X < (0x4 << 10) MFP_DSMSK > +#define MFP_DS08X < (0x5 << 10) MFP_DSMSK > +#define MFP_DS10X < (0x6 << 10) MFP_DSMSK > +#define MFP_DS13X < (0x7 << 10) MFP_DSMSK > + +/* + * MFP low power mode for pins. + * Example of use: + * pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL); + * + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) + * + * Input 0 X(0) X(0) X(0) 0 + * Drive 0 0 0 0 X(1) 0 + * Drive 1 0 1 X(1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFP_LPM(x) < (x) MFP_LPM_MSK > + +#define MFP_LPM_MSK 0xe1f0 +#define MFP_LPM_INPUT 0x0000 +#define MFP_LPM_DRIVE_LOW 0x2000 +#define MFP_LPM_DRIVE_HIGH 0x4100 +#define MFP_LPM_PULL_LOW 0x2080 +#define MFP_LPM_PULL_HIGH 0x4180 +#define MFP_LPM_FLOAT 0x0080 + +#define MFP_LPM_EDGE_NONE 0x0000 +#define MFP_LPM_EDGE_RISE 0x0010 +#define MFP_LPM_EDGE_FALL 0x0020 +#define MFP_LPM_EDGE_BOTH 0x0030 + / { model = "Marvell PXA3xx familiy SoC"; compatible = "marvell,pxa3xx";