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mtd: spi-nor: spansion: Rework spi_nor_cypress_octal_dtr_enable()
Introduce template operation to remove code duplication. Split spi_nor_cypress_octal_dtr_enable() in spi_nor_cypress_octal_dtr_ena() spi_nor_cypress_octal_dtr_dis() as it no longer made sense to try to keep everything alltogether: too many "if (enable)" throughout the code, which made the code difficult to read. Add debug messages in case spi_nor_read_id() fails. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220420103427.47867-9-tudor.ambarus@microchip.com
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@ -23,6 +23,88 @@
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0
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#define SPINOR_OP_CYPRESS_RD_FAST 0xee
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/* Cypress SPI NOR flash operations. */
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#define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \
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SPI_MEM_OP_ADDR(naddr, addr, 0), \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
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static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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/* Use 24 dummy cycles for memory array reads. */
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*buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR2V, 1, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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nor->read_dummy = 24;
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/* Set the octal and DTR enable bits. */
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buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(3, SPINOR_REG_CYPRESS_CFR5V, 1, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);
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if (ret) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
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return ret;
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}
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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return 0;
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}
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static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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/*
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* The register is 1-byte wide, but 1-byte transactions are not allowed
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* in 8D-8D-8D mode. Since there is no register at the next location,
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* just initialize the value to 0 and let the transaction go on.
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*/
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buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
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buf[1] = 0;
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op = (struct spi_mem_op)
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CYPRESS_NOR_WR_ANY_REG_OP(4, SPINOR_REG_CYPRESS_CFR5V, 2, buf);
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ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
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if (ret) {
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dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
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return ret;
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}
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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return 0;
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}
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/**
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* cypress_nor_octal_dtr_enable() - Enable octal DTR on Cypress flashes.
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* @nor: pointer to a 'struct spi_nor'
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@ -35,80 +117,8 @@
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*/
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static int cypress_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
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{
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struct spi_mem_op op;
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u8 *buf = nor->bouncebuf;
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int ret;
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if (enable) {
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/* Use 24 dummy cycles for memory array reads. */
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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*buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24;
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V,
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1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(1, buf, 1));
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ret = spi_mem_exec_op(nor->spimem, &op);
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if (ret)
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return ret;
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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return ret;
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nor->read_dummy = 24;
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}
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/* Set/unset the octal and DTR enable bits. */
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ret = spi_nor_write_enable(nor);
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if (ret)
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return ret;
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if (enable) {
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buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN;
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} else {
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/*
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* The register is 1-byte wide, but 1-byte transactions are not
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* allowed in 8D-8D-8D mode. Since there is no register at the
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* next location, just initialize the value to 0 and let the
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* transaction go on.
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*/
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buf[0] = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS;
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buf[1] = 0;
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}
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op = (struct spi_mem_op)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1),
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SPI_MEM_OP_ADDR(enable ? 3 : 4,
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SPINOR_REG_CYPRESS_CFR5V,
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1),
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_OUT(enable ? 1 : 2, buf, 1));
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if (!enable)
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spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
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ret = spi_mem_exec_op(nor->spimem, &op);
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if (ret)
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return ret;
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/* Read flash ID to make sure the switch was successful. */
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if (enable)
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ret = spi_nor_read_id(nor, 4, 3, buf, SNOR_PROTO_8_8_8_DTR);
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else
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ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
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if (ret)
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return ret;
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if (memcmp(buf, nor->info->id, nor->info->id_len))
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return -EINVAL;
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return 0;
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return enable ? cypress_nor_octal_dtr_en(nor) :
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cypress_nor_octal_dtr_dis(nor);
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}
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static void s28hs512t_default_init(struct spi_nor *nor)
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