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mmc: sdhci: put together into one condition checking
value of ios->timing is not related with SDCHI v3.0. If Controller version is v3.0, SDHCI_QUIRK_NO_HISPD_BIT is meaningless. To prevent the setting wrong bit moves into one condition checking. (e.g sdhci-s3c doesn't use SDHCI_CTRL_HISPD bit, instead using this bit as other purpose.) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -1623,7 +1623,14 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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if ((ios->timing == MMC_TIMING_SD_HS ||
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ios->timing == MMC_TIMING_MMC_HS)
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ios->timing == MMC_TIMING_MMC_HS ||
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ios->timing == MMC_TIMING_MMC_HS400 ||
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ios->timing == MMC_TIMING_MMC_HS200 ||
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ios->timing == MMC_TIMING_MMC_DDR52 ||
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ios->timing == MMC_TIMING_UHS_SDR50 ||
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ios->timing == MMC_TIMING_UHS_SDR104 ||
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ios->timing == MMC_TIMING_UHS_DDR50 ||
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ios->timing == MMC_TIMING_UHS_SDR25)
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&& !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
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ctrl |= SDHCI_CTRL_HISPD;
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else
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@ -1632,16 +1639,6 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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if (host->version >= SDHCI_SPEC_300) {
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u16 clk, ctrl_2;
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/* In case of UHS-I modes, set High Speed Enable */
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if ((ios->timing == MMC_TIMING_MMC_HS400) ||
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(ios->timing == MMC_TIMING_MMC_HS200) ||
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(ios->timing == MMC_TIMING_MMC_DDR52) ||
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(ios->timing == MMC_TIMING_UHS_SDR50) ||
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(ios->timing == MMC_TIMING_UHS_SDR104) ||
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(ios->timing == MMC_TIMING_UHS_DDR50) ||
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(ios->timing == MMC_TIMING_UHS_SDR25))
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ctrl |= SDHCI_CTRL_HISPD;
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if (!host->preset_enabled) {
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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/*
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