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drm/i915: PLL defines for VLV
Add register definitions for the new VLV PLL bits. v2: remove unused bits & regs (Ben) Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -796,7 +796,9 @@
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#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
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#define DPLL_VCO_ENABLE (1 << 31)
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#define DPLL_DVO_HIGH_SPEED (1 << 30)
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#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
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#define DPLL_SYNCLOCK_ENABLE (1 << 29)
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#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
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#define DPLL_VGA_MODE_DIS (1 << 28)
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#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
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#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
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@ -808,6 +810,7 @@
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#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
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#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
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#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
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#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
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#define SRX_INDEX 0x3c4
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#define SRX_DATA 0x3c5
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@ -903,6 +906,7 @@
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#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
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#define _DPLL_B_MD 0x06020 /* 965+ only */
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#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
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#define _FPA0 0x06040
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#define _FPA1 0x06044
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#define _FPB0 0x06048
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@ -3487,6 +3487,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
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return true;
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}
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static int valleyview_get_display_clock_speed(struct drm_device *dev)
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{
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return 400000; /* FIXME */
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}
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static int i945_get_display_clock_speed(struct drm_device *dev)
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{
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return 400000;
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@ -8987,7 +8992,10 @@ static void intel_init_display(struct drm_device *dev)
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}
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/* Returns the core display clock speed */
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if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
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if (IS_VALLEYVIEW(dev))
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dev_priv->display.get_display_clock_speed =
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valleyview_get_display_clock_speed;
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else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
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dev_priv->display.get_display_clock_speed =
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i945_get_display_clock_speed;
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else if (IS_I915G(dev))
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