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ARM: perf: use integers for ARMv7 event indices

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This patch ensures that integers are used to represent event indices in
the ARMv7 PMU backend. This ensures consistency between functions and
also with the arm_pmu structure.

Acked-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2011-07-19 22:17:48 +01:00
parent 6330aae7dc
commit 25e29c7c0f
1 changed files with 6 additions and 6 deletions
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12
arch/arm/kernel/perf_event_v7.c
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@ -793,7 +793,7 @@ static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc,
return ret;
}
static inline int armv7_pmnc_select_counter(unsigned int idx)
static inline int armv7_pmnc_select_counter(int idx)
{
u32 val;
@ -840,7 +840,7 @@ static inline void armv7pmu_write_counter(int idx, u32 value)
smp_processor_id(), idx);
}
static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
{
if (armv7_pmnc_select_counter(idx) == idx) {
val &= ARMV7_EVTSEL_MASK;
@ -848,7 +848,7 @@ static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
}
}
static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
static inline int armv7_pmnc_enable_counter(int idx)
{
u32 val;
@ -869,7 +869,7 @@ static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
return idx;
}
static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
static inline int armv7_pmnc_disable_counter(int idx)
{
u32 val;
@ -891,7 +891,7 @@ static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
return idx;
}
static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
static inline int armv7_pmnc_enable_intens(int idx)
{
u32 val;
@ -912,7 +912,7 @@ static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
return idx;
}
static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
static inline int armv7_pmnc_disable_intens(int idx)
{
u32 val;