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PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
Instead of using the switch case statement to enable/disable the reference clock handled by this driver itself, let's introduce a new callback enable_ref_clk() and define it for platforms that require it. This simplifies the code. Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-5-b68ee5ef2b4d@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Frank Li
Krzysztof Wilczyński
parent
d657ea28d5
commit
256867b746
@ -101,6 +101,7 @@ struct imx_pcie_drvdata {
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const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
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const struct pci_epc_features *epc_features;
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int (*init_phy)(struct imx_pcie *pcie);
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int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
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};
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struct imx_pcie {
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@ -582,21 +583,20 @@ static int imx_pcie_attach_pd(struct device *dev)
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return 0;
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}
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static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
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static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
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{
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unsigned int offset;
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int ret = 0;
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if (enable)
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regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
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switch (imx_pcie->drvdata->variant) {
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case IMX6SX:
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
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break;
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case IMX6QP:
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case IMX6Q:
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return 0;
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}
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static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
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{
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if (enable) {
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/* power up core phy and enable ref clock */
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
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regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
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/*
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* the async reset input need ref clock to sync internally,
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* when the ref clock comes after reset, internal synced
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@ -604,55 +604,33 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie)
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* add one ~10us delay here.
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*/
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usleep_range(10, 100);
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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break;
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case IMX7D:
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case IMX95:
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case IMX95_EP:
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break;
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case IMX8MM:
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case IMX8MM_EP:
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case IMX8MQ:
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case IMX8MQ_EP:
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case IMX8MP:
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case IMX8MP_EP:
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offset = imx_pcie_grp_offset(imx_pcie);
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/*
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* Set the over ride low and enabled
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* make sure that REF_CLK is turned on.
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*/
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regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
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IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
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0);
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regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
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IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
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IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
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break;
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regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
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} else {
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regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
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regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
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}
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return ret;
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return 0;
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}
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static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie)
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static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
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{
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switch (imx_pcie->drvdata->variant) {
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case IMX6QP:
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case IMX6Q:
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD,
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IMX6Q_GPR1_PCIE_TEST_PD);
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break;
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case IMX7D:
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regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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break;
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default:
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break;
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int offset = imx_pcie_grp_offset(imx_pcie);
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if (enable) {
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regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
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regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
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}
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return 0;
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}
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static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
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{
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if (!enable)
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regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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return 0;
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}
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static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
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@ -665,10 +643,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
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if (ret)
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return ret;
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ret = imx_pcie_enable_ref_clk(imx_pcie);
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if (ret) {
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dev_err(dev, "unable to enable pcie ref clock\n");
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goto err_ref_clk;
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if (imx_pcie->drvdata->enable_ref_clk) {
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ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true);
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if (ret) {
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dev_err(dev, "Failed to enable PCIe REFCLK\n");
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goto err_ref_clk;
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}
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}
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/* allow the clocks to stabilize */
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@ -683,7 +663,8 @@ err_ref_clk:
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static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
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{
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imx_pcie_disable_ref_clk(imx_pcie);
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if (imx_pcie->drvdata->enable_ref_clk)
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imx_pcie->drvdata->enable_ref_clk(imx_pcie, false);
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clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
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}
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@ -1459,6 +1440,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.init_phy = imx_pcie_init_phy,
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.enable_ref_clk = imx6q_pcie_enable_ref_clk,
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},
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[IMX6SX] = {
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.variant = IMX6SX,
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@ -1473,6 +1455,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.init_phy = imx6sx_pcie_init_phy,
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.enable_ref_clk = imx6sx_pcie_enable_ref_clk,
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},
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[IMX6QP] = {
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.variant = IMX6QP,
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@ -1488,6 +1471,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.init_phy = imx_pcie_init_phy,
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.enable_ref_clk = imx6q_pcie_enable_ref_clk,
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},
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[IMX7D] = {
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.variant = IMX7D,
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@ -1500,6 +1484,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.init_phy = imx7d_pcie_init_phy,
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.enable_ref_clk = imx7d_pcie_enable_ref_clk,
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},
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[IMX8MQ] = {
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.variant = IMX8MQ,
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@ -1513,6 +1498,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[1] = IOMUXC_GPR12,
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.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
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.init_phy = imx8mq_pcie_init_phy,
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.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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@ -1524,6 +1510,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
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},
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[IMX8MP] = {
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.variant = IMX8MP,
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@ -1535,6 +1522,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
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},
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[IMX95] = {
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.variant = IMX95,
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@ -1561,6 +1549,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
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.epc_features = &imx8m_pcie_epc_features,
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.init_phy = imx8mq_pcie_init_phy,
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.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
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},
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[IMX8MM_EP] = {
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.variant = IMX8MM_EP,
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@ -1573,6 +1562,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.epc_features = &imx8m_pcie_epc_features,
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.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
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},
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[IMX8MP_EP] = {
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.variant = IMX8MP_EP,
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@ -1585,6 +1575,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
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.mode_off[0] = IOMUXC_GPR12,
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.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
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.epc_features = &imx8m_pcie_epc_features,
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.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
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},
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[IMX95_EP] = {
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.variant = IMX95_EP,
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