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KVM VMX changes for 6.5:
- Fix missing/incorrect #GP checks on ENCLS - Use standard mmu_notifier hooks for handling APIC access page - Misc cleanups -----BEGIN PGP SIGNATURE----- iQJGBAABCgAwFiEEMHr+pfEFOIzK+KY1YJEiAU0MEvkFAmSaLDYSHHNlYW5qY0Bn b29nbGUuY29tAAoJEGCRIgFNDBL5ovYP/ib86UG9QXwoEKx0mIyLQ5q1jD+StvxH 18SIH62+MXAtmz2E+EmXIySW76diOKCngApJ11WTERPwpZYEpcITh2D2Jp/vwgk5 xUPK+WKYQs1SGpJu3wXhLE1u6mB7X9p7EaXRSKG67P7YK09gTaOik1/3h6oNrGO+ KI06reCQN1PstKTfrZXxYpRlfDc761YaAmSZ79Bg+bK9PisFqme7TJ2mAqNZPFPd E7ho/UOEyWRSyd5VMsuOUB760pMQ9edKrs+38xNDp5N+0Fh0ItTjuAcd2KVWMZyW Fk+CJq4kCqTlEik5OwcEHsTGJGBFscGPSO+T0YtVfSZDdtN/rHN7l8RGquOebVTG Ldm5bg4agu4lXsqqzMxn8J9SkbNg3xno79mMSc2185jS2HLt5Hu6PzQnQ2tEtHJQ IuovmssHOVKDoYODOg0tq8UMydgT3hAvC7YJCouubCjxUUw+22nhN3EDuAhbJhtT DgQNGT7GmsrKIWLEjbm6EpLLOdJdB7/U1MrEshLS015a/DUz4b3ZGYApneifJL8h nGE2Wu+36xGUVNLgDMdvd+R17WdyQa+f+9KjUGy71KelFV4vI4A3JwvH0aIsTyHZ LGlQBZqelc66GYwMiqVC0GYGRtrdgygQopfstvZJ3rYiHZV/mdhB5A0T4J2Xvh2Q bnDNzsSFdsH5 =PjYj -----END PGP SIGNATURE----- Merge tag 'kvm-x86-vmx-6.5' of https://github.com/kvm-x86/linux into HEAD KVM VMX changes for 6.5: - Fix missing/incorrect #GP checks on ENCLS - Use standard mmu_notifier hooks for handling APIC access page - Misc cleanups
This commit is contained in:
commit
255006adb3
@ -1603,6 +1603,10 @@ bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
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if (tdp_mmu_enabled)
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flush = kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
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if (kvm_x86_ops.set_apic_access_page_addr &&
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range->slot->id == APIC_ACCESS_PAGE_PRIVATE_MEMSLOT)
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kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
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return flush;
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}
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@ -152,8 +152,8 @@ static inline bool cpu_has_vmx_ept(void)
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static inline bool vmx_umip_emulated(void)
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{
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return vmcs_config.cpu_based_2nd_exec_ctrl &
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SECONDARY_EXEC_DESC;
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return !boot_cpu_has(X86_FEATURE_UMIP) &&
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(vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_DESC);
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}
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static inline bool cpu_has_vmx_rdtscp(void)
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@ -2328,8 +2328,7 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct loaded_vmcs *vmcs0
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* Preset *DT exiting when emulating UMIP, so that vmx_set_cr4()
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* will not have to rewrite the controls just for this bit.
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*/
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if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated() &&
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(vmcs12->guest_cr4 & X86_CR4_UMIP))
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if (vmx_umip_emulated() && (vmcs12->guest_cr4 & X86_CR4_UMIP))
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exec_control |= SECONDARY_EXEC_DESC;
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if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
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@ -385,8 +385,6 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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}
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break;
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case MSR_IA32_DS_AREA:
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if (msr_info->host_initiated && data && !guest_cpuid_has(vcpu, X86_FEATURE_DS))
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return 1;
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if (is_noncanonical_address(data, vcpu))
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return 1;
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@ -357,11 +357,12 @@ static int handle_encls_einit(struct kvm_vcpu *vcpu)
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static inline bool encls_leaf_enabled_in_guest(struct kvm_vcpu *vcpu, u32 leaf)
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{
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if (!enable_sgx || !guest_cpuid_has(vcpu, X86_FEATURE_SGX))
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return false;
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/*
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* ENCLS generates a #UD if SGX1 isn't supported, i.e. this point will
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* be reached if and only if the SGX1 leafs are enabled.
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*/
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if (leaf >= ECREATE && leaf <= ETRACK)
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return guest_cpuid_has(vcpu, X86_FEATURE_SGX1);
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return true;
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if (leaf >= EAUG && leaf <= EMODT)
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return guest_cpuid_has(vcpu, X86_FEATURE_SGX2);
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@ -380,9 +381,11 @@ int handle_encls(struct kvm_vcpu *vcpu)
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{
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u32 leaf = (u32)kvm_rax_read(vcpu);
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if (!encls_leaf_enabled_in_guest(vcpu, leaf)) {
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if (!enable_sgx || !guest_cpuid_has(vcpu, X86_FEATURE_SGX) ||
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!guest_cpuid_has(vcpu, X86_FEATURE_SGX1)) {
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kvm_queue_exception(vcpu, UD_VECTOR);
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} else if (!sgx_enabled_in_guest_bios(vcpu)) {
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} else if (!encls_leaf_enabled_in_guest(vcpu, leaf) ||
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!sgx_enabled_in_guest_bios(vcpu) || !is_paging(vcpu)) {
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kvm_inject_gp(vcpu, 0);
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} else {
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if (leaf == ECREATE)
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@ -187,7 +187,7 @@ SYM_FUNC_START(__vmx_vcpu_run)
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_ASM_EXTABLE(.Lvmresume, .Lfixup)
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_ASM_EXTABLE(.Lvmlaunch, .Lfixup)
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SYM_INNER_LABEL(vmx_vmexit, SYM_L_GLOBAL)
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SYM_INNER_LABEL_ALIGN(vmx_vmexit, SYM_L_GLOBAL)
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/* Restore unwind state from before the VMRESUME/VMLAUNCH. */
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UNWIND_HINT_RESTORE
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@ -3384,15 +3384,15 @@ static bool vmx_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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{
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unsigned long old_cr4 = vcpu->arch.cr4;
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unsigned long old_cr4 = kvm_read_cr4(vcpu);
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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unsigned long hw_cr4;
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/*
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* Pass through host's Machine Check Enable value to hw_cr4, which
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* is in force while we are in guest mode. Do not let guests control
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* this bit, even if host CR4.MCE == 0.
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*/
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unsigned long hw_cr4;
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hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
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if (is_unrestricted_guest(vcpu))
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hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
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@ -3401,7 +3401,7 @@ void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
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else
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hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
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if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
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if (vmx_umip_emulated()) {
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if (cr4 & X86_CR4_UMIP) {
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secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC);
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hw_cr4 &= ~X86_CR4_UMIP;
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@ -5399,7 +5399,13 @@ static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
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static int handle_desc(struct kvm_vcpu *vcpu)
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{
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WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
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/*
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* UMIP emulation relies on intercepting writes to CR4.UMIP, i.e. this
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* and other code needs to be updated if UMIP can be guest owned.
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*/
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BUILD_BUG_ON(KVM_POSSIBLE_CR4_GUEST_BITS & X86_CR4_UMIP);
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WARN_ON_ONCE(!kvm_is_cr4_bit_set(vcpu, X86_CR4_UMIP));
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return kvm_emulate_instruction(vcpu, 0);
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}
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@ -6705,7 +6711,12 @@ void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
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static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
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{
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struct page *page;
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const gfn_t gfn = APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT;
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struct kvm *kvm = vcpu->kvm;
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struct kvm_memslots *slots = kvm_memslots(kvm);
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struct kvm_memory_slot *slot;
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unsigned long mmu_seq;
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kvm_pfn_t pfn;
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/* Defer reload until vmcs01 is the current VMCS. */
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if (is_guest_mode(vcpu)) {
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@ -6717,18 +6728,53 @@ static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu)
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SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
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return;
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page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
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if (is_error_page(page))
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/*
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* Grab the memslot so that the hva lookup for the mmu_notifier retry
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* is guaranteed to use the same memslot as the pfn lookup, i.e. rely
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* on the pfn lookup's validation of the memslot to ensure a valid hva
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* is used for the retry check.
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*/
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slot = id_to_memslot(slots, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT);
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if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
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return;
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vmcs_write64(APIC_ACCESS_ADDR, page_to_phys(page));
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/*
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* Ensure that the mmu_notifier sequence count is read before KVM
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* retrieves the pfn from the primary MMU. Note, the memslot is
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* protected by SRCU, not the mmu_notifier. Pairs with the smp_wmb()
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* in kvm_mmu_invalidate_end().
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*/
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mmu_seq = kvm->mmu_invalidate_seq;
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smp_rmb();
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/*
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* No need to retry if the memslot does not exist or is invalid. KVM
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* controls the APIC-access page memslot, and only deletes the memslot
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* if APICv is permanently inhibited, i.e. the memslot won't reappear.
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*/
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pfn = gfn_to_pfn_memslot(slot, gfn);
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if (is_error_noslot_pfn(pfn))
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return;
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read_lock(&vcpu->kvm->mmu_lock);
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if (mmu_invalidate_retry_hva(kvm, mmu_seq,
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gfn_to_hva_memslot(slot, gfn))) {
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kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
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read_unlock(&vcpu->kvm->mmu_lock);
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goto out;
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}
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vmcs_write64(APIC_ACCESS_ADDR, pfn_to_hpa(pfn));
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read_unlock(&vcpu->kvm->mmu_lock);
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vmx_flush_tlb_current(vcpu);
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out:
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/*
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* Do not pin apic access page in memory, the MMU notifier
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* will call us again if it is migrated or swapped out.
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*/
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put_page(page);
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kvm_release_pfn_clean(pfn);
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}
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static void vmx_hwapic_isr_update(int max_isr)
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@ -10449,20 +10449,6 @@ static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
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vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
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}
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void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
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unsigned long start, unsigned long end)
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{
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unsigned long apic_address;
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/*
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* The physical address of apic access page is stored in the VMCS.
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* Update it when it becomes invalid.
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*/
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apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
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if (start <= apic_address && apic_address < end)
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kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
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}
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void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
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{
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static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
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@ -2239,9 +2239,6 @@ static inline long kvm_arch_vcpu_async_ioctl(struct file *filp,
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}
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#endif /* CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL */
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void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
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unsigned long start, unsigned long end);
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void kvm_arch_guest_memory_reclaimed(struct kvm *kvm);
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#ifdef CONFIG_HAVE_KVM_VCPU_RUN_PID_CHANGE
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@ -154,11 +154,6 @@ static unsigned long long kvm_active_vms;
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static DEFINE_PER_CPU(cpumask_var_t, cpu_kick_mask);
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__weak void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
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unsigned long start, unsigned long end)
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{
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}
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__weak void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
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{
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}
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@ -521,18 +516,6 @@ static inline struct kvm *mmu_notifier_to_kvm(struct mmu_notifier *mn)
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return container_of(mn, struct kvm, mmu_notifier);
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}
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static void kvm_mmu_notifier_invalidate_range(struct mmu_notifier *mn,
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struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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struct kvm *kvm = mmu_notifier_to_kvm(mn);
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int idx;
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idx = srcu_read_lock(&kvm->srcu);
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kvm_arch_mmu_notifier_invalidate_range(kvm, start, end);
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srcu_read_unlock(&kvm->srcu, idx);
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}
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typedef bool (*hva_handler_t)(struct kvm *kvm, struct kvm_gfn_range *range);
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typedef void (*on_lock_fn_t)(struct kvm *kvm, unsigned long start,
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@ -910,7 +893,6 @@ static void kvm_mmu_notifier_release(struct mmu_notifier *mn,
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}
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static const struct mmu_notifier_ops kvm_mmu_notifier_ops = {
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.invalidate_range = kvm_mmu_notifier_invalidate_range,
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.invalidate_range_start = kvm_mmu_notifier_invalidate_range_start,
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.invalidate_range_end = kvm_mmu_notifier_invalidate_range_end,
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.clear_flush_young = kvm_mmu_notifier_clear_flush_young,
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