mirror of
https://github.com/torvalds/linux.git
synced 2024-11-24 21:21:41 +00:00
Merge branch 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
* 'drm-nouveau-fixes' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nouveau: init vblank requests list drm/nv50: extend vblank semaphore to generic dmaobj + offset pair drm/nouveau: mark most of our ioctls as deprecated, move to compat layer drm/nouveau: move current gpuobj code out of nouveau_object.c drm/nouveau/gem: fix object reference leak in a failure path drm/nv50: rename INVALID_QUERY_OR_TEXTURE error to INVALID_OPERATION drm/nv84: decode PCRYPT errors drm/nouveau: dcb table quirk for fdo#50830 nouveau: Fix alignment requirements on src and dst addresses
This commit is contained in:
Dave Airlie
commit
2536f7dc42
@ -4,7 +4,7 @@
|
||||
|
||||
ccflags-y := -Iinclude/drm
|
||||
nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
|
||||
nouveau_object.o nouveau_irq.o nouveau_notifier.o \
|
||||
nouveau_gpuobj.o nouveau_irq.o nouveau_notifier.o \
|
||||
nouveau_sgdma.o nouveau_dma.o nouveau_util.o \
|
||||
nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
|
||||
nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
|
||||
@ -12,6 +12,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
|
||||
nouveau_hdmi.o nouveau_dp.o nouveau_ramht.o \
|
||||
nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \
|
||||
nouveau_mm.o nouveau_vm.o nouveau_mxm.o nouveau_gpio.o \
|
||||
nouveau_abi16.o \
|
||||
nv04_timer.o \
|
||||
nv04_mc.o nv40_mc.o nv50_mc.o \
|
||||
nv04_fb.o nv10_fb.o nv20_fb.o nv30_fb.o nv40_fb.o \
|
||||
|
||||
245
drivers/gpu/drm/nouveau/nouveau_abi16.c
Normal file
245
drivers/gpu/drm/nouveau/nouveau_abi16.c
Normal file
@ -0,0 +1,245 @@
|
||||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_abi16.h"
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#include "nouveau_ramht.h"
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#include "nouveau_software.h"
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|
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int
|
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nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS)
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||||
{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_nouveau_getparam *getparam = data;
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|
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switch (getparam->param) {
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case NOUVEAU_GETPARAM_CHIPSET_ID:
|
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getparam->value = dev_priv->chipset;
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break;
|
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case NOUVEAU_GETPARAM_PCI_VENDOR:
|
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getparam->value = dev->pci_vendor;
|
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break;
|
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case NOUVEAU_GETPARAM_PCI_DEVICE:
|
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getparam->value = dev->pci_device;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_BUS_TYPE:
|
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if (drm_pci_device_is_agp(dev))
|
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getparam->value = 0;
|
||||
else
|
||||
if (!pci_is_pcie(dev->pdev))
|
||||
getparam->value = 1;
|
||||
else
|
||||
getparam->value = 2;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_FB_SIZE:
|
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getparam->value = dev_priv->fb_available_size;
|
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break;
|
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case NOUVEAU_GETPARAM_AGP_SIZE:
|
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getparam->value = dev_priv->gart_info.aper_size;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_VM_VRAM_BASE:
|
||||
getparam->value = 0; /* deprecated */
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_PTIMER_TIME:
|
||||
getparam->value = dev_priv->engine.timer.read(dev);
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_HAS_BO_USAGE:
|
||||
getparam->value = 1;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
|
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getparam->value = 1;
|
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break;
|
||||
case NOUVEAU_GETPARAM_GRAPH_UNITS:
|
||||
/* NV40 and NV50 versions are quite different, but register
|
||||
* address is the same. User is supposed to know the card
|
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* family anyway... */
|
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if (dev_priv->chipset >= 0x40) {
|
||||
getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
|
||||
break;
|
||||
}
|
||||
/* FALLTHRU */
|
||||
default:
|
||||
NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
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nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
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struct drm_nouveau_channel_alloc *init = data;
|
||||
struct nouveau_channel *chan;
|
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int ret;
|
||||
|
||||
if (!dev_priv->eng[NVOBJ_ENGINE_GR])
|
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return -ENODEV;
|
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|
||||
if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
|
||||
return -EINVAL;
|
||||
|
||||
ret = nouveau_channel_alloc(dev, &chan, file_priv,
|
||||
init->fb_ctxdma_handle,
|
||||
init->tt_ctxdma_handle);
|
||||
if (ret)
|
||||
return ret;
|
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init->channel = chan->id;
|
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|
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if (nouveau_vram_pushbuf == 0) {
|
||||
if (chan->dma.ib_max)
|
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init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
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NOUVEAU_GEM_DOMAIN_GART;
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else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
|
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init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
|
||||
else
|
||||
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
|
||||
} else {
|
||||
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
|
||||
}
|
||||
|
||||
if (dev_priv->card_type < NV_C0) {
|
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init->subchan[0].handle = 0x00000000;
|
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init->subchan[0].grclass = 0x0000;
|
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init->subchan[1].handle = NvSw;
|
||||
init->subchan[1].grclass = NV_SW;
|
||||
init->nr_subchan = 2;
|
||||
}
|
||||
|
||||
/* Named memory object area */
|
||||
ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
|
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&init->notifier_handle);
|
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|
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if (ret == 0)
|
||||
atomic_inc(&chan->users); /* userspace reference */
|
||||
nouveau_channel_put(&chan);
|
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return ret;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS)
|
||||
{
|
||||
struct drm_nouveau_channel_free *req = data;
|
||||
struct nouveau_channel *chan;
|
||||
|
||||
chan = nouveau_channel_get(file_priv, req->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
list_del(&chan->list);
|
||||
atomic_dec(&chan->users);
|
||||
nouveau_channel_put(&chan);
|
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return 0;
|
||||
}
|
||||
|
||||
int
|
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nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS)
|
||||
{
|
||||
struct drm_nouveau_grobj_alloc *init = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
if (init->handle == ~0)
|
||||
return -EINVAL;
|
||||
|
||||
/* compatibility with userspace that assumes 506e for all chipsets */
|
||||
if (init->class == 0x506e) {
|
||||
init->class = nouveau_software_class(dev);
|
||||
if (init->class == 0x906e)
|
||||
return 0;
|
||||
} else
|
||||
if (init->class == 0x906e) {
|
||||
NV_ERROR(dev, "906e not supported yet\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
chan = nouveau_channel_get(file_priv, init->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
if (nouveau_ramht_find(chan, init->handle)) {
|
||||
ret = -EEXIST;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
|
||||
if (ret) {
|
||||
NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
|
||||
ret, init->channel, init->handle);
|
||||
}
|
||||
|
||||
out:
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
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struct drm_nouveau_notifierobj_alloc *na = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
/* completely unnecessary for these chipsets... */
|
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if (unlikely(dev_priv->card_type >= NV_C0))
|
||||
return -EINVAL;
|
||||
|
||||
chan = nouveau_channel_get(file_priv, na->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
|
||||
&na->offset);
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS)
|
||||
{
|
||||
struct drm_nouveau_gpuobj_free *objfree = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
chan = nouveau_channel_get(file_priv, objfree->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
/* Synchronize with the user channel */
|
||||
nouveau_channel_idle(chan);
|
||||
|
||||
ret = nouveau_ramht_remove(chan, objfree->handle);
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
83
drivers/gpu/drm/nouveau/nouveau_abi16.h
Normal file
83
drivers/gpu/drm/nouveau/nouveau_abi16.h
Normal file
@ -0,0 +1,83 @@
|
||||
#ifndef __NOUVEAU_ABI16_H__
|
||||
#define __NOUVEAU_ABI16_H__
|
||||
|
||||
#define ABI16_IOCTL_ARGS \
|
||||
struct drm_device *dev, void *data, struct drm_file *file_priv
|
||||
int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
|
||||
int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
|
||||
int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
|
||||
int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
|
||||
int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
|
||||
int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS);
|
||||
int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS);
|
||||
|
||||
struct drm_nouveau_channel_alloc {
|
||||
uint32_t fb_ctxdma_handle;
|
||||
uint32_t tt_ctxdma_handle;
|
||||
|
||||
int channel;
|
||||
uint32_t pushbuf_domains;
|
||||
|
||||
/* Notifier memory */
|
||||
uint32_t notifier_handle;
|
||||
|
||||
/* DRM-enforced subchannel assignments */
|
||||
struct {
|
||||
uint32_t handle;
|
||||
uint32_t grclass;
|
||||
} subchan[8];
|
||||
uint32_t nr_subchan;
|
||||
};
|
||||
|
||||
struct drm_nouveau_channel_free {
|
||||
int channel;
|
||||
};
|
||||
|
||||
struct drm_nouveau_grobj_alloc {
|
||||
int channel;
|
||||
uint32_t handle;
|
||||
int class;
|
||||
};
|
||||
|
||||
struct drm_nouveau_notifierobj_alloc {
|
||||
uint32_t channel;
|
||||
uint32_t handle;
|
||||
uint32_t size;
|
||||
uint32_t offset;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gpuobj_free {
|
||||
int channel;
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GETPARAM_PCI_VENDOR 3
|
||||
#define NOUVEAU_GETPARAM_PCI_DEVICE 4
|
||||
#define NOUVEAU_GETPARAM_BUS_TYPE 5
|
||||
#define NOUVEAU_GETPARAM_FB_SIZE 8
|
||||
#define NOUVEAU_GETPARAM_AGP_SIZE 9
|
||||
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
|
||||
#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
|
||||
#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
|
||||
#define NOUVEAU_GETPARAM_PTIMER_TIME 14
|
||||
#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
|
||||
#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
|
||||
struct drm_nouveau_getparam {
|
||||
uint64_t param;
|
||||
uint64_t value;
|
||||
};
|
||||
|
||||
struct drm_nouveau_setparam {
|
||||
uint64_t param;
|
||||
uint64_t value;
|
||||
};
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
|
||||
#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
|
||||
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
|
||||
#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
|
||||
|
||||
#endif
|
||||
@ -6091,6 +6091,18 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
|
||||
}
|
||||
}
|
||||
|
||||
/* fdo#50830: connector indices for VGA and DVI-I are backwards */
|
||||
if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) {
|
||||
if (idx == 0 && *conn == 0x02000300)
|
||||
*conn = 0x02011300;
|
||||
else
|
||||
if (idx == 1 && *conn == 0x04011310)
|
||||
*conn = 0x04000310;
|
||||
else
|
||||
if (idx == 2 && *conn == 0x02011312)
|
||||
*conn = 0x02000312;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@ -395,98 +395,3 @@ nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
|
||||
nouveau_channel_put(&chan);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/***********************************
|
||||
* ioctls wrapping the functions
|
||||
***********************************/
|
||||
|
||||
static int
|
||||
nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct drm_nouveau_channel_alloc *init = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
if (!dev_priv->eng[NVOBJ_ENGINE_GR])
|
||||
return -ENODEV;
|
||||
|
||||
if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
|
||||
return -EINVAL;
|
||||
|
||||
ret = nouveau_channel_alloc(dev, &chan, file_priv,
|
||||
init->fb_ctxdma_handle,
|
||||
init->tt_ctxdma_handle);
|
||||
if (ret)
|
||||
return ret;
|
||||
init->channel = chan->id;
|
||||
|
||||
if (nouveau_vram_pushbuf == 0) {
|
||||
if (chan->dma.ib_max)
|
||||
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
|
||||
NOUVEAU_GEM_DOMAIN_GART;
|
||||
else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
|
||||
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
|
||||
else
|
||||
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
|
||||
} else {
|
||||
init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
|
||||
}
|
||||
|
||||
if (dev_priv->card_type < NV_C0) {
|
||||
init->subchan[0].handle = 0x00000000;
|
||||
init->subchan[0].grclass = 0x0000;
|
||||
init->subchan[1].handle = NvSw;
|
||||
init->subchan[1].grclass = NV_SW;
|
||||
init->nr_subchan = 2;
|
||||
}
|
||||
|
||||
/* Named memory object area */
|
||||
ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
|
||||
&init->notifier_handle);
|
||||
|
||||
if (ret == 0)
|
||||
atomic_inc(&chan->users); /* userspace reference */
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_channel_free *req = data;
|
||||
struct nouveau_channel *chan;
|
||||
|
||||
chan = nouveau_channel_get(file_priv, req->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
list_del(&chan->list);
|
||||
atomic_dec(&chan->users);
|
||||
nouveau_channel_put(&chan);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***********************************
|
||||
* finally, the ioctl table
|
||||
***********************************/
|
||||
|
||||
struct drm_ioctl_desc nouveau_ioctls[] = {
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
|
||||
};
|
||||
|
||||
int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
#include "drm.h"
|
||||
#include "drm_crtc_helper.h"
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_abi16.h"
|
||||
#include "nouveau_hw.h"
|
||||
#include "nouveau_fb.h"
|
||||
#include "nouveau_fbcon.h"
|
||||
@ -384,6 +385,21 @@ nouveau_pci_resume(struct pci_dev *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct drm_ioctl_desc nouveau_ioctls[] = {
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
|
||||
DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
|
||||
};
|
||||
|
||||
static const struct file_operations nouveau_driver_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = drm_open,
|
||||
@ -462,7 +478,7 @@ static struct pci_driver nouveau_pci_driver = {
|
||||
|
||||
static int __init nouveau_init(void)
|
||||
{
|
||||
driver.num_ioctls = nouveau_max_ioctl;
|
||||
driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
|
||||
|
||||
if (nouveau_modeset == -1) {
|
||||
#ifdef CONFIG_VGA_CONSOLE
|
||||
|
||||
@ -689,8 +689,6 @@ struct drm_nouveau_private {
|
||||
void (*irq_handler[32])(struct drm_device *);
|
||||
bool msi_enabled;
|
||||
|
||||
struct list_head vbl_waiting;
|
||||
|
||||
struct {
|
||||
struct drm_global_reference mem_global_ref;
|
||||
struct ttm_bo_global_ref bo_global_ref;
|
||||
@ -872,10 +870,6 @@ extern int nouveau_load(struct drm_device *, unsigned long flags);
|
||||
extern int nouveau_firstopen(struct drm_device *);
|
||||
extern void nouveau_lastclose(struct drm_device *);
|
||||
extern int nouveau_unload(struct drm_device *);
|
||||
extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
|
||||
struct drm_file *);
|
||||
extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
|
||||
struct drm_file *);
|
||||
extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
|
||||
uint32_t reg, uint32_t mask, uint32_t val);
|
||||
extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
|
||||
@ -914,15 +908,8 @@ extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
|
||||
extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
|
||||
int cout, uint32_t start, uint32_t end,
|
||||
uint32_t *offset);
|
||||
extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
|
||||
extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
|
||||
struct drm_file *);
|
||||
extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
|
||||
struct drm_file *);
|
||||
|
||||
/* nouveau_channel.c */
|
||||
extern struct drm_ioctl_desc nouveau_ioctls[];
|
||||
extern int nouveau_max_ioctl;
|
||||
extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
|
||||
extern int nouveau_channel_alloc(struct drm_device *dev,
|
||||
struct nouveau_channel **chan,
|
||||
@ -938,7 +925,7 @@ extern void nouveau_channel_ref(struct nouveau_channel *chan,
|
||||
struct nouveau_channel **pchan);
|
||||
extern int nouveau_channel_idle(struct nouveau_channel *chan);
|
||||
|
||||
/* nouveau_object.c */
|
||||
/* nouveau_gpuobj.c */
|
||||
#define NVOBJ_ENGINE_ADD(d, e, p) do { \
|
||||
struct drm_nouveau_private *dev_priv = (d)->dev_private; \
|
||||
dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
|
||||
@ -993,10 +980,6 @@ extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
|
||||
extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
|
||||
int class, u64 base, u64 size, int target,
|
||||
int access, u32 type, u32 comp);
|
||||
extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
|
||||
struct drm_file *);
|
||||
extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
|
||||
struct drm_file *);
|
||||
|
||||
/* nouveau_irq.c */
|
||||
extern int nouveau_irq_init(struct drm_device *);
|
||||
|
||||
@ -341,6 +341,7 @@ retry:
|
||||
if (nvbo->reserved_by && nvbo->reserved_by == file_priv) {
|
||||
NV_ERROR(dev, "multiple instances of buffer %d on "
|
||||
"validation list\n", b->handle);
|
||||
drm_gem_object_unreference_unlocked(gem);
|
||||
validate_fini(op, NULL);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -758,66 +758,6 @@ nouveau_gpuobj_resume(struct drm_device *dev)
|
||||
dev_priv->engine.instmem.flush(dev);
|
||||
}
|
||||
|
||||
int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_grobj_alloc *init = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
if (init->handle == ~0)
|
||||
return -EINVAL;
|
||||
|
||||
/* compatibility with userspace that assumes 506e for all chipsets */
|
||||
if (init->class == 0x506e) {
|
||||
init->class = nouveau_software_class(dev);
|
||||
if (init->class == 0x906e)
|
||||
return 0;
|
||||
} else
|
||||
if (init->class == 0x906e) {
|
||||
NV_ERROR(dev, "906e not supported yet\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
chan = nouveau_channel_get(file_priv, init->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
if (nouveau_ramht_find(chan, init->handle)) {
|
||||
ret = -EEXIST;
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = nouveau_gpuobj_gr_new(chan, init->handle, init->class);
|
||||
if (ret) {
|
||||
NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n",
|
||||
ret, init->channel, init->handle);
|
||||
}
|
||||
|
||||
out:
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_gpuobj_free *objfree = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
chan = nouveau_channel_get(file_priv, objfree->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
/* Synchronize with the user channel */
|
||||
nouveau_channel_idle(chan);
|
||||
|
||||
ret = nouveau_ramht_remove(chan, objfree->handle);
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
|
||||
u32
|
||||
nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
|
||||
{
|
||||
@ -41,12 +41,8 @@
|
||||
void
|
||||
nouveau_irq_preinstall(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
/* Master disable */
|
||||
nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
|
||||
|
||||
INIT_LIST_HEAD(&dev_priv->vbl_waiting);
|
||||
}
|
||||
|
||||
int
|
||||
|
||||
@ -161,44 +161,3 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
|
||||
*b_offset = mem->start;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_notifier_offset(struct nouveau_gpuobj *nobj, uint32_t *poffset)
|
||||
{
|
||||
if (!nobj || nobj->dtor != nouveau_notifier_gpuobj_dtor)
|
||||
return -EINVAL;
|
||||
|
||||
if (poffset) {
|
||||
struct drm_mm_node *mem = nobj->priv;
|
||||
|
||||
if (*poffset >= mem->size)
|
||||
return false;
|
||||
|
||||
*poffset += mem->start;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_ioctl_notifier_alloc(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct drm_nouveau_notifierobj_alloc *na = data;
|
||||
struct nouveau_channel *chan;
|
||||
int ret;
|
||||
|
||||
/* completely unnecessary for these chipsets... */
|
||||
if (unlikely(dev_priv->card_type >= NV_C0))
|
||||
return -EINVAL;
|
||||
|
||||
chan = nouveau_channel_get(file_priv, na->channel);
|
||||
if (IS_ERR(chan))
|
||||
return PTR_ERR(chan);
|
||||
|
||||
ret = nouveau_notifier_alloc(chan, na->handle, na->size, 0, 0x1000,
|
||||
&na->offset);
|
||||
nouveau_channel_put(&chan);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -4,46 +4,33 @@
|
||||
struct nouveau_software_priv {
|
||||
struct nouveau_exec_engine base;
|
||||
struct list_head vblank;
|
||||
spinlock_t peephole_lock;
|
||||
};
|
||||
|
||||
struct nouveau_software_chan {
|
||||
struct list_head flip;
|
||||
struct {
|
||||
struct list_head list;
|
||||
struct nouveau_bo *bo;
|
||||
u32 channel;
|
||||
u32 ctxdma;
|
||||
u32 offset;
|
||||
u32 value;
|
||||
u32 head;
|
||||
} vblank;
|
||||
};
|
||||
|
||||
static inline void
|
||||
nouveau_software_vblank(struct drm_device *dev, int crtc)
|
||||
{
|
||||
struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
|
||||
struct nouveau_software_chan *pch, *tmp;
|
||||
|
||||
list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
|
||||
if (pch->vblank.head != crtc)
|
||||
continue;
|
||||
|
||||
nouveau_bo_wr32(pch->vblank.bo, pch->vblank.offset,
|
||||
pch->vblank.value);
|
||||
list_del(&pch->vblank.list);
|
||||
drm_vblank_put(dev, crtc);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
nouveau_software_context_new(struct nouveau_software_chan *pch)
|
||||
{
|
||||
INIT_LIST_HEAD(&pch->flip);
|
||||
INIT_LIST_HEAD(&pch->vblank.list);
|
||||
}
|
||||
|
||||
static inline void
|
||||
nouveau_software_create(struct nouveau_software_priv *psw)
|
||||
{
|
||||
INIT_LIST_HEAD(&psw->vblank);
|
||||
spin_lock_init(&psw->peephole_lock);
|
||||
}
|
||||
|
||||
static inline u16
|
||||
|
||||
@ -1234,80 +1234,6 @@ int nouveau_unload(struct drm_device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct drm_nouveau_getparam *getparam = data;
|
||||
|
||||
switch (getparam->param) {
|
||||
case NOUVEAU_GETPARAM_CHIPSET_ID:
|
||||
getparam->value = dev_priv->chipset;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_PCI_VENDOR:
|
||||
getparam->value = dev->pci_vendor;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_PCI_DEVICE:
|
||||
getparam->value = dev->pci_device;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_BUS_TYPE:
|
||||
if (drm_pci_device_is_agp(dev))
|
||||
getparam->value = NV_AGP;
|
||||
else if (pci_is_pcie(dev->pdev))
|
||||
getparam->value = NV_PCIE;
|
||||
else
|
||||
getparam->value = NV_PCI;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_FB_SIZE:
|
||||
getparam->value = dev_priv->fb_available_size;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_AGP_SIZE:
|
||||
getparam->value = dev_priv->gart_info.aper_size;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_VM_VRAM_BASE:
|
||||
getparam->value = 0; /* deprecated */
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_PTIMER_TIME:
|
||||
getparam->value = dev_priv->engine.timer.read(dev);
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_HAS_BO_USAGE:
|
||||
getparam->value = 1;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
|
||||
getparam->value = 1;
|
||||
break;
|
||||
case NOUVEAU_GETPARAM_GRAPH_UNITS:
|
||||
/* NV40 and NV50 versions are quite different, but register
|
||||
* address is the same. User is supposed to know the card
|
||||
* family anyway... */
|
||||
if (dev_priv->chipset >= 0x40) {
|
||||
getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
|
||||
break;
|
||||
}
|
||||
/* FALLTHRU */
|
||||
default:
|
||||
NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
nouveau_ioctl_setparam(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv)
|
||||
{
|
||||
struct drm_nouveau_setparam *setparam = data;
|
||||
|
||||
switch (setparam->param) {
|
||||
default:
|
||||
NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Wait until (value(reg) & mask) == val, up until timeout has hit */
|
||||
bool
|
||||
nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
|
||||
|
||||
@ -646,7 +646,30 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
|
||||
static void
|
||||
nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
|
||||
{
|
||||
nouveau_software_vblank(dev, crtc);
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
|
||||
struct nouveau_software_chan *pch, *tmp;
|
||||
|
||||
list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
|
||||
if (pch->vblank.head != crtc)
|
||||
continue;
|
||||
|
||||
spin_lock(&psw->peephole_lock);
|
||||
nv_wr32(dev, 0x001704, pch->vblank.channel);
|
||||
nv_wr32(dev, 0x001710, 0x80000000 | pch->vblank.ctxdma);
|
||||
if (dev_priv->chipset == 0x50) {
|
||||
nv_wr32(dev, 0x001570, pch->vblank.offset);
|
||||
nv_wr32(dev, 0x001574, pch->vblank.value);
|
||||
} else {
|
||||
nv_wr32(dev, 0x060010, pch->vblank.offset);
|
||||
nv_wr32(dev, 0x060014, pch->vblank.value);
|
||||
}
|
||||
spin_unlock(&psw->peephole_lock);
|
||||
|
||||
list_del(&pch->vblank.list);
|
||||
drm_vblank_put(dev, crtc);
|
||||
}
|
||||
|
||||
drm_handle_vblank(dev, crtc);
|
||||
}
|
||||
|
||||
|
||||
@ -299,7 +299,7 @@ static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
|
||||
|
||||
/* There must be a *lot* of these. Will take some time to gather them up. */
|
||||
struct nouveau_enum nv50_data_error_names[] = {
|
||||
{ 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
|
||||
{ 0x00000003, "INVALID_OPERATION", NULL },
|
||||
{ 0x00000004, "INVALID_VALUE", NULL },
|
||||
{ 0x00000005, "INVALID_ENUM", NULL },
|
||||
{ 0x00000008, "INVALID_OBJECT", NULL },
|
||||
|
||||
@ -36,9 +36,6 @@ struct nv50_software_priv {
|
||||
|
||||
struct nv50_software_chan {
|
||||
struct nouveau_software_chan base;
|
||||
struct {
|
||||
struct nouveau_gpuobj *object;
|
||||
} vblank;
|
||||
};
|
||||
|
||||
static int
|
||||
@ -51,11 +48,7 @@ mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
if (!gpuobj)
|
||||
return -ENOENT;
|
||||
|
||||
if (nouveau_notifier_offset(gpuobj, NULL))
|
||||
return -EINVAL;
|
||||
|
||||
pch->vblank.object = gpuobj;
|
||||
pch->base.vblank.offset = ~0;
|
||||
pch->base.vblank.ctxdma = gpuobj->cinst >> 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -63,11 +56,7 @@ static int
|
||||
mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
|
||||
|
||||
if (nouveau_notifier_offset(pch->vblank.object, &data))
|
||||
return -ERANGE;
|
||||
|
||||
pch->base.vblank.offset = data >> 2;
|
||||
pch->base.vblank.offset = data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -86,7 +75,7 @@ mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
|
||||
struct drm_device *dev = chan->dev;
|
||||
|
||||
if (!pch->vblank.object || pch->base.vblank.offset == ~0 || data > 1)
|
||||
if (data > 1)
|
||||
return -EINVAL;
|
||||
|
||||
drm_vblank_get(dev, data);
|
||||
@ -116,7 +105,7 @@ nv50_software_context_new(struct nouveau_channel *chan, int engine)
|
||||
return -ENOMEM;
|
||||
|
||||
nouveau_software_context_new(&pch->base);
|
||||
pch->base.vblank.bo = chan->notifier_bo;
|
||||
pch->base.vblank.channel = chan->ramin->vinst >> 12;
|
||||
chan->engctx[engine] = pch;
|
||||
|
||||
/* dma objects for display sync channel semaphore blocks */
|
||||
|
||||
@ -117,18 +117,30 @@ nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
|
||||
nv50_vm_flush_engine(dev, 0x0a);
|
||||
}
|
||||
|
||||
static struct nouveau_bitfield nv84_crypt_intr[] = {
|
||||
{ 0x00000001, "INVALID_STATE" },
|
||||
{ 0x00000002, "ILLEGAL_MTHD" },
|
||||
{ 0x00000004, "ILLEGAL_CLASS" },
|
||||
{ 0x00000080, "QUERY" },
|
||||
{ 0x00000100, "FAULT" },
|
||||
{}
|
||||
};
|
||||
|
||||
static void
|
||||
nv84_crypt_isr(struct drm_device *dev)
|
||||
{
|
||||
u32 stat = nv_rd32(dev, 0x102130);
|
||||
u32 mthd = nv_rd32(dev, 0x102190);
|
||||
u32 data = nv_rd32(dev, 0x102194);
|
||||
u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
|
||||
u64 inst = (u64)(nv_rd32(dev, 0x102188) & 0x7fffffff) << 12;
|
||||
int show = nouveau_ratelimit();
|
||||
int chid = nv50_graph_isr_chid(dev, inst);
|
||||
|
||||
if (show) {
|
||||
NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
||||
stat, mthd, data, inst);
|
||||
NV_INFO(dev, "PCRYPT:");
|
||||
nouveau_bitfield_print(nv84_crypt_intr, stat);
|
||||
printk(KERN_CONT " ch %d (0x%010llx) mthd 0x%04x data 0x%08x\n",
|
||||
chid, inst, mthd, data);
|
||||
}
|
||||
|
||||
nv_wr32(dev, 0x102130, stat);
|
||||
|
||||
@ -119,9 +119,9 @@ dispatch_dma:
|
||||
// mthd 0x030c-0x0340, various stuff
|
||||
.b16 0xc3 14
|
||||
.b32 #ctx_src_address_high ~0x000000ff
|
||||
.b32 #ctx_src_address_low ~0xfffffff0
|
||||
.b32 #ctx_src_address_low ~0xffffffff
|
||||
.b32 #ctx_dst_address_high ~0x000000ff
|
||||
.b32 #ctx_dst_address_low ~0xfffffff0
|
||||
.b32 #ctx_dst_address_low ~0xffffffff
|
||||
.b32 #ctx_src_pitch ~0x0007ffff
|
||||
.b32 #ctx_dst_pitch ~0x0007ffff
|
||||
.b32 #ctx_xcnt ~0x0000ffff
|
||||
|
||||
@ -1,37 +1,72 @@
|
||||
uint32_t nva3_pcopy_data[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
u32 nva3_pcopy_data[] = {
|
||||
/* 0x0000: ctx_object */
|
||||
0x00000000,
|
||||
/* 0x0004: ctx_dma */
|
||||
/* 0x0004: ctx_dma_query */
|
||||
0x00000000,
|
||||
/* 0x0008: ctx_dma_src */
|
||||
0x00000000,
|
||||
/* 0x000c: ctx_dma_dst */
|
||||
0x00000000,
|
||||
/* 0x0010: ctx_query_address_high */
|
||||
0x00000000,
|
||||
/* 0x0014: ctx_query_address_low */
|
||||
0x00000000,
|
||||
/* 0x0018: ctx_query_counter */
|
||||
0x00000000,
|
||||
/* 0x001c: ctx_src_address_high */
|
||||
0x00000000,
|
||||
/* 0x0020: ctx_src_address_low */
|
||||
0x00000000,
|
||||
/* 0x0024: ctx_src_pitch */
|
||||
0x00000000,
|
||||
/* 0x0028: ctx_src_tile_mode */
|
||||
0x00000000,
|
||||
/* 0x002c: ctx_src_xsize */
|
||||
0x00000000,
|
||||
/* 0x0030: ctx_src_ysize */
|
||||
0x00000000,
|
||||
/* 0x0034: ctx_src_zsize */
|
||||
0x00000000,
|
||||
/* 0x0038: ctx_src_zoff */
|
||||
0x00000000,
|
||||
/* 0x003c: ctx_src_xoff */
|
||||
0x00000000,
|
||||
/* 0x0040: ctx_src_yoff */
|
||||
0x00000000,
|
||||
/* 0x0044: ctx_src_cpp */
|
||||
0x00000000,
|
||||
/* 0x0048: ctx_dst_address_high */
|
||||
0x00000000,
|
||||
/* 0x004c: ctx_dst_address_low */
|
||||
0x00000000,
|
||||
/* 0x0050: ctx_dst_pitch */
|
||||
0x00000000,
|
||||
/* 0x0054: ctx_dst_tile_mode */
|
||||
0x00000000,
|
||||
/* 0x0058: ctx_dst_xsize */
|
||||
0x00000000,
|
||||
/* 0x005c: ctx_dst_ysize */
|
||||
0x00000000,
|
||||
/* 0x0060: ctx_dst_zsize */
|
||||
0x00000000,
|
||||
/* 0x0064: ctx_dst_zoff */
|
||||
0x00000000,
|
||||
/* 0x0068: ctx_dst_xoff */
|
||||
0x00000000,
|
||||
/* 0x006c: ctx_dst_yoff */
|
||||
0x00000000,
|
||||
/* 0x0070: ctx_dst_cpp */
|
||||
0x00000000,
|
||||
/* 0x0074: ctx_format */
|
||||
0x00000000,
|
||||
/* 0x0078: ctx_swz_const0 */
|
||||
0x00000000,
|
||||
/* 0x007c: ctx_swz_const1 */
|
||||
0x00000000,
|
||||
/* 0x0080: ctx_xcnt */
|
||||
0x00000000,
|
||||
/* 0x0084: ctx_ycnt */
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -63,6 +98,7 @@ uint32_t nva3_pcopy_data[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
/* 0x0100: dispatch_table */
|
||||
0x00010000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -73,6 +109,7 @@ uint32_t nva3_pcopy_data[] = {
|
||||
0x00010162,
|
||||
0x00000000,
|
||||
0x00030060,
|
||||
/* 0x0128: dispatch_dma */
|
||||
0x00010170,
|
||||
0x00000000,
|
||||
0x00010170,
|
||||
@ -118,11 +155,11 @@ uint32_t nva3_pcopy_data[] = {
|
||||
0x0000001c,
|
||||
0xffffff00,
|
||||
0x00000020,
|
||||
0x0000000f,
|
||||
0x00000000,
|
||||
0x00000048,
|
||||
0xffffff00,
|
||||
0x0000004c,
|
||||
0x0000000f,
|
||||
0x00000000,
|
||||
0x00000024,
|
||||
0xfff80000,
|
||||
0x00000050,
|
||||
@ -146,7 +183,8 @@ uint32_t nva3_pcopy_data[] = {
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
uint32_t nva3_pcopy_code[] = {
|
||||
u32 nva3_pcopy_code[] = {
|
||||
/* 0x0000: main */
|
||||
0x04fe04bd,
|
||||
0x3517f000,
|
||||
0xf10010fe,
|
||||
@ -158,23 +196,31 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x17f11031,
|
||||
0x27f01200,
|
||||
0x0012d003,
|
||||
/* 0x002f: spin */
|
||||
0xf40031f4,
|
||||
0x0ef40028,
|
||||
/* 0x0035: ih */
|
||||
0x8001cffd,
|
||||
0xf40812c4,
|
||||
0x21f4060b,
|
||||
/* 0x0041: ih_no_chsw */
|
||||
0x0412c472,
|
||||
0xf4060bf4,
|
||||
/* 0x004a: ih_no_cmd */
|
||||
0x11c4c321,
|
||||
0x4001d00c,
|
||||
/* 0x0052: swctx */
|
||||
0x47f101f8,
|
||||
0x4bfe7700,
|
||||
0x0007fe00,
|
||||
0xf00204b9,
|
||||
0x01f40643,
|
||||
0x0604fa09,
|
||||
/* 0x006b: swctx_load */
|
||||
0xfa060ef4,
|
||||
/* 0x006e: swctx_done */
|
||||
0x03f80504,
|
||||
/* 0x0072: chsw */
|
||||
0x27f100f8,
|
||||
0x23cf1400,
|
||||
0x1e3fc800,
|
||||
@ -183,18 +229,22 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x1e3af052,
|
||||
0xf00023d0,
|
||||
0x24d00147,
|
||||
/* 0x0093: chsw_no_unload */
|
||||
0xcf00f880,
|
||||
0x3dc84023,
|
||||
0x220bf41e,
|
||||
0xf40131f4,
|
||||
0x57f05221,
|
||||
0x0367f004,
|
||||
/* 0x00a8: chsw_load_ctx_dma */
|
||||
0xa07856bc,
|
||||
0xb6018068,
|
||||
0x87d00884,
|
||||
0x0162b600,
|
||||
/* 0x00bb: chsw_finish_load */
|
||||
0xf0f018f4,
|
||||
0x23d00237,
|
||||
/* 0x00c3: dispatch */
|
||||
0xf100f880,
|
||||
0xcf190037,
|
||||
0x33cf4032,
|
||||
@ -202,6 +252,7 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x1024b607,
|
||||
0x010057f1,
|
||||
0x74bd64bd,
|
||||
/* 0x00dc: dispatch_loop */
|
||||
0x58005658,
|
||||
0x50b60157,
|
||||
0x0446b804,
|
||||
@ -211,6 +262,7 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0xb60276bb,
|
||||
0x57bb0374,
|
||||
0xdf0ef400,
|
||||
/* 0x0100: dispatch_valid_mthd */
|
||||
0xb60246bb,
|
||||
0x45bb0344,
|
||||
0x01459800,
|
||||
@ -220,31 +272,41 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0xb0014658,
|
||||
0x1bf40064,
|
||||
0x00538009,
|
||||
/* 0x0127: dispatch_cmd */
|
||||
0xf4300ef4,
|
||||
0x55f90132,
|
||||
0xf40c01f4,
|
||||
/* 0x0132: dispatch_invalid_bitfield */
|
||||
0x25f0250e,
|
||||
/* 0x0135: dispatch_illegal_mthd */
|
||||
0x0125f002,
|
||||
/* 0x0138: dispatch_error */
|
||||
0x100047f1,
|
||||
0xd00042d0,
|
||||
0x27f04043,
|
||||
0x0002d040,
|
||||
/* 0x0148: hostirq_wait */
|
||||
0xf08002cf,
|
||||
0x24b04024,
|
||||
0xf71bf400,
|
||||
/* 0x0154: dispatch_done */
|
||||
0x1d0027f1,
|
||||
0xd00137f0,
|
||||
0x00f80023,
|
||||
/* 0x0160: cmd_nop */
|
||||
/* 0x0162: cmd_pm_trigger */
|
||||
0x27f100f8,
|
||||
0x34bd2200,
|
||||
0xd00233f0,
|
||||
0x00f80023,
|
||||
/* 0x0170: cmd_dma */
|
||||
0x012842b7,
|
||||
0xf00145b6,
|
||||
0x43801e39,
|
||||
0x0040b701,
|
||||
0x0644b606,
|
||||
0xf80043d0,
|
||||
/* 0x0189: cmd_exec_set_format */
|
||||
0xf030f400,
|
||||
0xb00001b0,
|
||||
0x01b00101,
|
||||
@ -256,20 +318,26 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x70b63847,
|
||||
0x0232f401,
|
||||
0x94bd84bd,
|
||||
/* 0x01b4: ncomp_loop */
|
||||
0xb60f4ac4,
|
||||
0xb4bd0445,
|
||||
/* 0x01bc: bpc_loop */
|
||||
0xf404a430,
|
||||
0xa5ff0f18,
|
||||
0x00cbbbc0,
|
||||
0xf40231f4,
|
||||
/* 0x01ce: cmp_c0 */
|
||||
0x1bf4220e,
|
||||
0x10c7f00c,
|
||||
0xf400cbbb,
|
||||
/* 0x01da: cmp_c1 */
|
||||
0xa430160e,
|
||||
0x0c18f406,
|
||||
0xbb14c7f0,
|
||||
0x0ef400cb,
|
||||
/* 0x01e9: cmp_zero */
|
||||
0x80c7f107,
|
||||
/* 0x01ed: bpc_next */
|
||||
0x01c83800,
|
||||
0xb60180b6,
|
||||
0xb5b801b0,
|
||||
@ -280,6 +348,7 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x98110680,
|
||||
0x68fd2008,
|
||||
0x0502f400,
|
||||
/* 0x0216: dst_xcnt */
|
||||
0x75fd64bd,
|
||||
0x1c078000,
|
||||
0xf10078fd,
|
||||
@ -304,6 +373,7 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x980056d0,
|
||||
0x56d01f06,
|
||||
0x1030f440,
|
||||
/* 0x0276: cmd_exec_set_surface_tiled */
|
||||
0x579800f8,
|
||||
0x6879c70a,
|
||||
0xb66478c7,
|
||||
@ -311,9 +381,11 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x0e76b060,
|
||||
0xf0091bf4,
|
||||
0x0ef40477,
|
||||
/* 0x0291: xtile64 */
|
||||
0x027cf00f,
|
||||
0xfd1170b6,
|
||||
0x77f00947,
|
||||
/* 0x029d: xtileok */
|
||||
0x0f5a9806,
|
||||
0xfd115b98,
|
||||
0xb7f000ab,
|
||||
@ -371,6 +443,7 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x67d00600,
|
||||
0x0060b700,
|
||||
0x0068d004,
|
||||
/* 0x0382: cmd_exec_set_surface_linear */
|
||||
0x6cf000f8,
|
||||
0x0260b702,
|
||||
0x0864b602,
|
||||
@ -381,13 +454,16 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0xb70067d0,
|
||||
0x98040060,
|
||||
0x67d00957,
|
||||
/* 0x03ab: cmd_exec_wait */
|
||||
0xf900f800,
|
||||
0xf110f900,
|
||||
0xb6080007,
|
||||
/* 0x03b6: loop */
|
||||
0x01cf0604,
|
||||
0x0114f000,
|
||||
0xfcfa1bf4,
|
||||
0xf800fc10,
|
||||
/* 0x03c5: cmd_exec_query */
|
||||
0x0d34c800,
|
||||
0xf5701bf4,
|
||||
0xf103ab21,
|
||||
@ -417,6 +493,7 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x47f10153,
|
||||
0x44b60800,
|
||||
0x0045d006,
|
||||
/* 0x0438: query_counter */
|
||||
0x03ab21f5,
|
||||
0x080c47f1,
|
||||
0x980644b6,
|
||||
@ -439,11 +516,13 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x47f10153,
|
||||
0x44b60800,
|
||||
0x0045d006,
|
||||
/* 0x0492: cmd_exec */
|
||||
0x21f500f8,
|
||||
0x3fc803ab,
|
||||
0x0e0bf400,
|
||||
0x018921f5,
|
||||
0x020047f1,
|
||||
/* 0x04a7: cmd_exec_no_format */
|
||||
0xf11e0ef4,
|
||||
0xb6081067,
|
||||
0x77f00664,
|
||||
@ -451,19 +530,24 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0x981c0780,
|
||||
0x67d02007,
|
||||
0x4067d000,
|
||||
/* 0x04c2: cmd_exec_init_src_surface */
|
||||
0x32f444bd,
|
||||
0xc854bd02,
|
||||
0x0bf4043f,
|
||||
0x8221f50a,
|
||||
0x0a0ef403,
|
||||
/* 0x04d4: src_tiled */
|
||||
0x027621f5,
|
||||
/* 0x04db: cmd_exec_init_dst_surface */
|
||||
0xf40749f0,
|
||||
0x57f00231,
|
||||
0x083fc82c,
|
||||
0xf50a0bf4,
|
||||
0xf4038221,
|
||||
/* 0x04ee: dst_tiled */
|
||||
0x21f50a0e,
|
||||
0x49f00276,
|
||||
/* 0x04f5: cmd_exec_kick */
|
||||
0x0057f108,
|
||||
0x0654b608,
|
||||
0xd0210698,
|
||||
@ -473,6 +557,8 @@ uint32_t nva3_pcopy_code[] = {
|
||||
0xc80054d0,
|
||||
0x0bf40c3f,
|
||||
0xc521f507,
|
||||
/* 0x0519: cmd_exec_done */
|
||||
/* 0x051b: cmd_wrcache_flush */
|
||||
0xf100f803,
|
||||
0xbd220027,
|
||||
0x0133f034,
|
||||
|
||||
@ -1,34 +1,65 @@
|
||||
uint32_t nvc0_pcopy_data[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
u32 nvc0_pcopy_data[] = {
|
||||
/* 0x0000: ctx_object */
|
||||
0x00000000,
|
||||
/* 0x0004: ctx_query_address_high */
|
||||
0x00000000,
|
||||
/* 0x0008: ctx_query_address_low */
|
||||
0x00000000,
|
||||
/* 0x000c: ctx_query_counter */
|
||||
0x00000000,
|
||||
/* 0x0010: ctx_src_address_high */
|
||||
0x00000000,
|
||||
/* 0x0014: ctx_src_address_low */
|
||||
0x00000000,
|
||||
/* 0x0018: ctx_src_pitch */
|
||||
0x00000000,
|
||||
/* 0x001c: ctx_src_tile_mode */
|
||||
0x00000000,
|
||||
/* 0x0020: ctx_src_xsize */
|
||||
0x00000000,
|
||||
/* 0x0024: ctx_src_ysize */
|
||||
0x00000000,
|
||||
/* 0x0028: ctx_src_zsize */
|
||||
0x00000000,
|
||||
/* 0x002c: ctx_src_zoff */
|
||||
0x00000000,
|
||||
/* 0x0030: ctx_src_xoff */
|
||||
0x00000000,
|
||||
/* 0x0034: ctx_src_yoff */
|
||||
0x00000000,
|
||||
/* 0x0038: ctx_src_cpp */
|
||||
0x00000000,
|
||||
/* 0x003c: ctx_dst_address_high */
|
||||
0x00000000,
|
||||
/* 0x0040: ctx_dst_address_low */
|
||||
0x00000000,
|
||||
/* 0x0044: ctx_dst_pitch */
|
||||
0x00000000,
|
||||
/* 0x0048: ctx_dst_tile_mode */
|
||||
0x00000000,
|
||||
/* 0x004c: ctx_dst_xsize */
|
||||
0x00000000,
|
||||
/* 0x0050: ctx_dst_ysize */
|
||||
0x00000000,
|
||||
/* 0x0054: ctx_dst_zsize */
|
||||
0x00000000,
|
||||
/* 0x0058: ctx_dst_zoff */
|
||||
0x00000000,
|
||||
/* 0x005c: ctx_dst_xoff */
|
||||
0x00000000,
|
||||
/* 0x0060: ctx_dst_yoff */
|
||||
0x00000000,
|
||||
/* 0x0064: ctx_dst_cpp */
|
||||
0x00000000,
|
||||
/* 0x0068: ctx_format */
|
||||
0x00000000,
|
||||
/* 0x006c: ctx_swz_const0 */
|
||||
0x00000000,
|
||||
/* 0x0070: ctx_swz_const1 */
|
||||
0x00000000,
|
||||
/* 0x0074: ctx_xcnt */
|
||||
0x00000000,
|
||||
/* 0x0078: ctx_ycnt */
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -63,6 +94,7 @@ uint32_t nvc0_pcopy_data[] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
/* 0x0100: dispatch_table */
|
||||
0x00010000,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
@ -111,11 +143,11 @@ uint32_t nvc0_pcopy_data[] = {
|
||||
0x00000010,
|
||||
0xffffff00,
|
||||
0x00000014,
|
||||
0x0000000f,
|
||||
0x00000000,
|
||||
0x0000003c,
|
||||
0xffffff00,
|
||||
0x00000040,
|
||||
0x0000000f,
|
||||
0x00000000,
|
||||
0x00000018,
|
||||
0xfff80000,
|
||||
0x00000044,
|
||||
@ -139,7 +171,8 @@ uint32_t nvc0_pcopy_data[] = {
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
uint32_t nvc0_pcopy_code[] = {
|
||||
u32 nvc0_pcopy_code[] = {
|
||||
/* 0x0000: main */
|
||||
0x04fe04bd,
|
||||
0x3517f000,
|
||||
0xf10010fe,
|
||||
@ -151,15 +184,20 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x17f11031,
|
||||
0x27f01200,
|
||||
0x0012d003,
|
||||
/* 0x002f: spin */
|
||||
0xf40031f4,
|
||||
0x0ef40028,
|
||||
/* 0x0035: ih */
|
||||
0x8001cffd,
|
||||
0xf40812c4,
|
||||
0x21f4060b,
|
||||
/* 0x0041: ih_no_chsw */
|
||||
0x0412c4ca,
|
||||
0xf5070bf4,
|
||||
/* 0x004b: ih_no_cmd */
|
||||
0xc4010221,
|
||||
0x01d00c11,
|
||||
/* 0x0053: swctx */
|
||||
0xf101f840,
|
||||
0xfe770047,
|
||||
0x47f1004b,
|
||||
@ -188,8 +226,11 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0xf00204b9,
|
||||
0x01f40643,
|
||||
0x0604fa09,
|
||||
/* 0x00c3: swctx_load */
|
||||
0xfa060ef4,
|
||||
/* 0x00c6: swctx_done */
|
||||
0x03f80504,
|
||||
/* 0x00ca: chsw */
|
||||
0x27f100f8,
|
||||
0x23cf1400,
|
||||
0x1e3fc800,
|
||||
@ -198,18 +239,22 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x1e3af053,
|
||||
0xf00023d0,
|
||||
0x24d00147,
|
||||
/* 0x00eb: chsw_no_unload */
|
||||
0xcf00f880,
|
||||
0x3dc84023,
|
||||
0x090bf41e,
|
||||
0xf40131f4,
|
||||
/* 0x00fa: chsw_finish_load */
|
||||
0x37f05321,
|
||||
0x8023d002,
|
||||
/* 0x0102: dispatch */
|
||||
0x37f100f8,
|
||||
0x32cf1900,
|
||||
0x0033cf40,
|
||||
0x07ff24e4,
|
||||
0xf11024b6,
|
||||
0xbd010057,
|
||||
/* 0x011b: dispatch_loop */
|
||||
0x5874bd64,
|
||||
0x57580056,
|
||||
0x0450b601,
|
||||
@ -219,6 +264,7 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0xbb0f08f4,
|
||||
0x74b60276,
|
||||
0x0057bb03,
|
||||
/* 0x013f: dispatch_valid_mthd */
|
||||
0xbbdf0ef4,
|
||||
0x44b60246,
|
||||
0x0045bb03,
|
||||
@ -229,24 +275,33 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x64b00146,
|
||||
0x091bf400,
|
||||
0xf4005380,
|
||||
/* 0x0166: dispatch_cmd */
|
||||
0x32f4300e,
|
||||
0xf455f901,
|
||||
0x0ef40c01,
|
||||
/* 0x0171: dispatch_invalid_bitfield */
|
||||
0x0225f025,
|
||||
/* 0x0174: dispatch_illegal_mthd */
|
||||
/* 0x0177: dispatch_error */
|
||||
0xf10125f0,
|
||||
0xd0100047,
|
||||
0x43d00042,
|
||||
0x4027f040,
|
||||
/* 0x0187: hostirq_wait */
|
||||
0xcf0002d0,
|
||||
0x24f08002,
|
||||
0x0024b040,
|
||||
/* 0x0193: dispatch_done */
|
||||
0xf1f71bf4,
|
||||
0xf01d0027,
|
||||
0x23d00137,
|
||||
/* 0x019f: cmd_nop */
|
||||
0xf800f800,
|
||||
/* 0x01a1: cmd_pm_trigger */
|
||||
0x0027f100,
|
||||
0xf034bd22,
|
||||
0x23d00233,
|
||||
/* 0x01af: cmd_exec_set_format */
|
||||
0xf400f800,
|
||||
0x01b0f030,
|
||||
0x0101b000,
|
||||
@ -258,20 +313,26 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x3847c701,
|
||||
0xf40170b6,
|
||||
0x84bd0232,
|
||||
/* 0x01da: ncomp_loop */
|
||||
0x4ac494bd,
|
||||
0x0445b60f,
|
||||
/* 0x01e2: bpc_loop */
|
||||
0xa430b4bd,
|
||||
0x0f18f404,
|
||||
0xbbc0a5ff,
|
||||
0x31f400cb,
|
||||
0x220ef402,
|
||||
/* 0x01f4: cmp_c0 */
|
||||
0xf00c1bf4,
|
||||
0xcbbb10c7,
|
||||
0x160ef400,
|
||||
/* 0x0200: cmp_c1 */
|
||||
0xf406a430,
|
||||
0xc7f00c18,
|
||||
0x00cbbb14,
|
||||
/* 0x020f: cmp_zero */
|
||||
0xf1070ef4,
|
||||
/* 0x0213: bpc_next */
|
||||
0x380080c7,
|
||||
0x80b601c8,
|
||||
0x01b0b601,
|
||||
@ -283,6 +344,7 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x1d08980e,
|
||||
0xf40068fd,
|
||||
0x64bd0502,
|
||||
/* 0x023c: dst_xcnt */
|
||||
0x800075fd,
|
||||
0x78fd1907,
|
||||
0x1057f100,
|
||||
@ -307,15 +369,18 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x1c069800,
|
||||
0xf44056d0,
|
||||
0x00f81030,
|
||||
/* 0x029c: cmd_exec_set_surface_tiled */
|
||||
0xc7075798,
|
||||
0x78c76879,
|
||||
0x0380b664,
|
||||
0xb06077c7,
|
||||
0x1bf40e76,
|
||||
0x0477f009,
|
||||
/* 0x02b7: xtile64 */
|
||||
0xf00f0ef4,
|
||||
0x70b6027c,
|
||||
0x0947fd11,
|
||||
/* 0x02c3: xtileok */
|
||||
0x980677f0,
|
||||
0x5b980c5a,
|
||||
0x00abfd0e,
|
||||
@ -374,6 +439,7 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0xb70067d0,
|
||||
0xd0040060,
|
||||
0x00f80068,
|
||||
/* 0x03a8: cmd_exec_set_surface_linear */
|
||||
0xb7026cf0,
|
||||
0xb6020260,
|
||||
0x57980864,
|
||||
@ -384,12 +450,15 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x0060b700,
|
||||
0x06579804,
|
||||
0xf80067d0,
|
||||
/* 0x03d1: cmd_exec_wait */
|
||||
0xf900f900,
|
||||
0x0007f110,
|
||||
0x0604b608,
|
||||
/* 0x03dc: loop */
|
||||
0xf00001cf,
|
||||
0x1bf40114,
|
||||
0xfc10fcfa,
|
||||
/* 0x03eb: cmd_exec_query */
|
||||
0xc800f800,
|
||||
0x1bf40d34,
|
||||
0xd121f570,
|
||||
@ -419,6 +488,7 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x0153f026,
|
||||
0x080047f1,
|
||||
0xd00644b6,
|
||||
/* 0x045e: query_counter */
|
||||
0x21f50045,
|
||||
0x47f103d1,
|
||||
0x44b6080c,
|
||||
@ -442,11 +512,13 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x080047f1,
|
||||
0xd00644b6,
|
||||
0x00f80045,
|
||||
/* 0x04b8: cmd_exec */
|
||||
0x03d121f5,
|
||||
0xf4003fc8,
|
||||
0x21f50e0b,
|
||||
0x47f101af,
|
||||
0x0ef40200,
|
||||
/* 0x04cd: cmd_exec_no_format */
|
||||
0x1067f11e,
|
||||
0x0664b608,
|
||||
0x800177f0,
|
||||
@ -454,18 +526,23 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x1d079819,
|
||||
0xd00067d0,
|
||||
0x44bd4067,
|
||||
/* 0x04e8: cmd_exec_init_src_surface */
|
||||
0xbd0232f4,
|
||||
0x043fc854,
|
||||
0xf50a0bf4,
|
||||
0xf403a821,
|
||||
/* 0x04fa: src_tiled */
|
||||
0x21f50a0e,
|
||||
0x49f0029c,
|
||||
/* 0x0501: cmd_exec_init_dst_surface */
|
||||
0x0231f407,
|
||||
0xc82c57f0,
|
||||
0x0bf4083f,
|
||||
0xa821f50a,
|
||||
0x0a0ef403,
|
||||
/* 0x0514: dst_tiled */
|
||||
0x029c21f5,
|
||||
/* 0x051b: cmd_exec_kick */
|
||||
0xf10849f0,
|
||||
0xb6080057,
|
||||
0x06980654,
|
||||
@ -475,7 +552,9 @@ uint32_t nvc0_pcopy_code[] = {
|
||||
0x54d00546,
|
||||
0x0c3fc800,
|
||||
0xf5070bf4,
|
||||
/* 0x053f: cmd_exec_done */
|
||||
0xf803eb21,
|
||||
/* 0x0541: cmd_wrcache_flush */
|
||||
0x0027f100,
|
||||
0xf034bd22,
|
||||
0x23d00133,
|
||||
|
||||
@ -25,70 +25,6 @@
|
||||
#ifndef __NOUVEAU_DRM_H__
|
||||
#define __NOUVEAU_DRM_H__
|
||||
|
||||
#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
|
||||
|
||||
struct drm_nouveau_channel_alloc {
|
||||
uint32_t fb_ctxdma_handle;
|
||||
uint32_t tt_ctxdma_handle;
|
||||
|
||||
int channel;
|
||||
uint32_t pushbuf_domains;
|
||||
|
||||
/* Notifier memory */
|
||||
uint32_t notifier_handle;
|
||||
|
||||
/* DRM-enforced subchannel assignments */
|
||||
struct {
|
||||
uint32_t handle;
|
||||
uint32_t grclass;
|
||||
} subchan[8];
|
||||
uint32_t nr_subchan;
|
||||
};
|
||||
|
||||
struct drm_nouveau_channel_free {
|
||||
int channel;
|
||||
};
|
||||
|
||||
struct drm_nouveau_grobj_alloc {
|
||||
int channel;
|
||||
uint32_t handle;
|
||||
int class;
|
||||
};
|
||||
|
||||
struct drm_nouveau_notifierobj_alloc {
|
||||
uint32_t channel;
|
||||
uint32_t handle;
|
||||
uint32_t size;
|
||||
uint32_t offset;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gpuobj_free {
|
||||
int channel;
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
/* FIXME : maybe unify {GET,SET}PARAMs */
|
||||
#define NOUVEAU_GETPARAM_PCI_VENDOR 3
|
||||
#define NOUVEAU_GETPARAM_PCI_DEVICE 4
|
||||
#define NOUVEAU_GETPARAM_BUS_TYPE 5
|
||||
#define NOUVEAU_GETPARAM_FB_SIZE 8
|
||||
#define NOUVEAU_GETPARAM_AGP_SIZE 9
|
||||
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
|
||||
#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
|
||||
#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
|
||||
#define NOUVEAU_GETPARAM_PTIMER_TIME 14
|
||||
#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
|
||||
#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
|
||||
struct drm_nouveau_getparam {
|
||||
uint64_t param;
|
||||
uint64_t value;
|
||||
};
|
||||
|
||||
struct drm_nouveau_setparam {
|
||||
uint64_t param;
|
||||
uint64_t value;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
|
||||
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
|
||||
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
|
||||
@ -180,35 +116,19 @@ struct drm_nouveau_gem_cpu_fini {
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
enum nouveau_bus_type {
|
||||
NV_AGP = 0,
|
||||
NV_PCI = 1,
|
||||
NV_PCIE = 2,
|
||||
};
|
||||
|
||||
struct drm_nouveau_sarea {
|
||||
};
|
||||
|
||||
#define DRM_NOUVEAU_GETPARAM 0x00
|
||||
#define DRM_NOUVEAU_SETPARAM 0x01
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x03
|
||||
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
|
||||
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
|
||||
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
|
||||
#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
|
||||
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
|
||||
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
|
||||
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
|
||||
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
|
||||
#define DRM_NOUVEAU_GEM_NEW 0x40
|
||||
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
|
||||
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
|
||||
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
|
||||
#define DRM_NOUVEAU_GEM_INFO 0x44
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
|
||||
#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam)
|
||||
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
|
||||
#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user