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ARM: imx: define gpt register offset per device type
It defines offset of gpt registers TSTAT, TCN and TCMP per device type in imx_gpt_data, so that these registers can be accessed in an way without timer_is_v2() checking. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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e510d2015d
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@ -96,6 +96,9 @@ struct imx_timer {
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};
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struct imx_gpt_data {
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int reg_tstat;
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int reg_tcn;
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int reg_tcmp;
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void (*gpt_setup_tctl)(struct imx_timer *imxtm);
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int (*set_next_event)(unsigned long evt,
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struct clock_event_device *ced);
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@ -159,7 +162,7 @@ static unsigned long imx_read_current_timer(void)
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static int __init mxc_clocksource_init(struct imx_timer *imxtm)
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{
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unsigned int c = clk_get_rate(imxtm->clk_per);
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void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
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void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
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imx_delay_timer.read_current_timer = &imx_read_current_timer;
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imx_delay_timer.freq = c;
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@ -227,13 +230,9 @@ static void mxc_set_mode(enum clock_event_mode mode,
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gpt_irq_disable();
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if (mode != imxtm->cem) {
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u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
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/* Set event time into far-far future */
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if (timer_is_v2())
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writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3,
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timer_base + V2_TCMP);
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else
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writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3,
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timer_base + MX1_2_TCMP);
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writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
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/* Clear pending interrupt */
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gpt_irq_acknowledge();
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@ -279,12 +278,10 @@ static void mxc_set_mode(enum clock_event_mode mode,
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ced = dev_id;
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struct imx_timer *imxtm = to_imx_timer(ced);
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uint32_t tstat;
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if (timer_is_v2())
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tstat = readl_relaxed(timer_base + V2_TSTAT);
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else
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tstat = readl_relaxed(timer_base + MX1_2_TSTAT);
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tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
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gpt_irq_acknowledge();
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@ -357,21 +354,33 @@ static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
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}
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static const struct imx_gpt_data imx1_gpt_data = {
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.reg_tstat = MX1_2_TSTAT,
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.reg_tcn = MX1_2_TCN,
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.reg_tcmp = MX1_2_TCMP,
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.gpt_setup_tctl = imx1_gpt_setup_tctl,
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.set_next_event = mx1_2_set_next_event,
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};
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static const struct imx_gpt_data imx21_gpt_data = {
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.reg_tstat = MX1_2_TSTAT,
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.reg_tcn = MX1_2_TCN,
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.reg_tcmp = MX1_2_TCMP,
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.gpt_setup_tctl = imx21_gpt_setup_tctl,
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.set_next_event = mx1_2_set_next_event,
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};
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static const struct imx_gpt_data imx31_gpt_data = {
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.reg_tstat = V2_TSTAT,
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.reg_tcn = V2_TCN,
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.reg_tcmp = V2_TCMP,
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.gpt_setup_tctl = imx31_gpt_setup_tctl,
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.set_next_event = v2_set_next_event,
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};
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static const struct imx_gpt_data imx6dl_gpt_data = {
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.reg_tstat = V2_TSTAT,
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.reg_tcn = V2_TCN,
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.reg_tcmp = V2_TCMP,
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.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
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.set_next_event = v2_set_next_event,
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};
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