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mtd: rawnand: hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC
This chip supports ONFI SDR timing mode 4, implement the new hook to advertize it. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200529111322.7184-26-miquel.raynal@bootlin.com
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@ -673,6 +673,15 @@ static void hynix_nand_cleanup(struct nand_chip *chip)
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nand_set_manufacturer_data(chip, NULL);
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}
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static int
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h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
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struct nand_interface_config *iface)
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{
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onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
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return nand_choose_best_sdr_timings(chip, iface, NULL);
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}
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static int hynix_nand_init(struct nand_chip *chip)
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{
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struct hynix_nand *hynix;
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@ -689,6 +698,11 @@ static int hynix_nand_init(struct nand_chip *chip)
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nand_set_manufacturer_data(chip, hynix);
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if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,
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sizeof("H27UCG8T2ATR-BC") - 1))
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chip->ops.choose_interface_config =
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h27ucg8t2atrbc_choose_interface_config;
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ret = hynix_nand_rr_init(chip);
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if (ret)
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hynix_nand_cleanup(chip);
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@ -50,7 +50,7 @@ struct nand_flash_dev nand_flash_ids[] = {
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{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
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{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
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SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
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NAND_ECC_INFO(40, SZ_1K), 4 },
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NAND_ECC_INFO(40, SZ_1K) },
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LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
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LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
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