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thunderbolt: Implement TMU time disruption for Intel Titan Ridge
Intel Titan Ridge based routers have slightly different flow for time disruption than USB4 compliant routers. This makes it work on Titan Ridge too. Needed to enable link low power states on Titan Ridge. Signed-off-by: Gil Fine <gil.fine@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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@ -2228,6 +2228,10 @@ struct tb_switch *tb_switch_alloc(struct tb *tb, struct device *parent,
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if (ret > 0)
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sw->cap_plug_events = ret;
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ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_TIME2);
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if (ret > 0)
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sw->cap_vsec_tmu = ret;
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ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_LINK_CONTROLLER);
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if (ret > 0)
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sw->cap_lc = ret;
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@ -138,6 +138,7 @@ enum tb_clx {
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* @link_usb4: Upstream link is USB4
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* @generation: Switch Thunderbolt generation
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* @cap_plug_events: Offset to the plug events capability (%0 if not found)
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* @cap_vsec_tmu: Offset to the TMU vendor specific capability (%0 if not found)
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* @cap_lc: Offset to the link controller capability (%0 if not found)
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* @is_unplugged: The switch is going away
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* @drom: DROM of the switch (%NULL if not found)
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@ -189,6 +190,7 @@ struct tb_switch {
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bool link_usb4;
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unsigned int generation;
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int cap_plug_events;
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int cap_vsec_tmu;
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int cap_lc;
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bool is_unplugged;
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u8 *drom;
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@ -446,6 +446,10 @@ struct tb_regs_hop {
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u32 unknown3:3; /* set to zero */
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} __packed;
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/* TMU Thunderbolt 3 registers */
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#define TB_TIME_VSEC_3_CS_26 0x1a
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#define TB_TIME_VSEC_3_CS_26_TD BIT(22)
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/* Common link controller registers */
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#define TB_LC_DESC 0x02
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#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
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@ -152,21 +152,27 @@ static int tb_port_tmu_time_sync_enable(struct tb_port *port)
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static int tb_switch_tmu_set_time_disruption(struct tb_switch *sw, bool set)
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{
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u32 val, offset, bit;
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int ret;
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u32 val;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_0, 1);
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if (tb_switch_is_usb4(sw)) {
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offset = sw->tmu.cap + TMU_RTR_CS_0;
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bit = TMU_RTR_CS_0_TD;
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} else {
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offset = sw->cap_vsec_tmu + TB_TIME_VSEC_3_CS_26;
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bit = TB_TIME_VSEC_3_CS_26_TD;
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}
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
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if (ret)
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return ret;
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if (set)
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val |= TMU_RTR_CS_0_TD;
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val |= bit;
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else
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val &= ~TMU_RTR_CS_0_TD;
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val &= ~bit;
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return tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_0, 1);
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return tb_sw_write(sw, &val, TB_CFG_SWITCH, offset, 1);
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}
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/**
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