Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-07 20:51:47 +00:00
Code Issues Packages Projects Releases Wiki Activity

drm/i915/dp: abstract training pattern selection

Browse Source 
Make it cleaner to add more checks in the function. No functional
changes.

Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org # dependency on the next patch
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1454667370-8001-1-git-send-email-jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2016-02-05 12:16:09 +02:00
parent 96afef1d5a
commit 23a5110dc6
1 changed files with 18 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/drm/i915/intel_dp_link_training.c
View File

@ -215,16 +215,15 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
} }
} }
static void /*
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
* or 1.2 devices that support it, Training Pattern 2 otherwise.
*/
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
{ {
bool channel_eq = false; u32 training_pattern = DP_TRAINING_PATTERN_2;
int tries, cr_tries;
uint32_t training_pattern = DP_TRAINING_PATTERN_2;
/* /*
* Training Pattern 3 for HBR2 or 1.2 devices that support it.
*
* Intel platforms that support HBR2 also support TPS3. TPS3 support is * Intel platforms that support HBR2 also support TPS3. TPS3 support is
* also mandatory for downstream devices that support HBR2. * also mandatory for downstream devices that support HBR2.
* *
@ -237,6 +236,18 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
else if (intel_dp->link_rate == 540000) else if (intel_dp->link_rate == 540000)
DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n"); DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
return training_pattern;
}
static void
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
{
bool channel_eq = false;
int tries, cr_tries;
u32 training_pattern;
training_pattern = intel_dp_training_pattern(intel_dp);
/* channel equalization */ /* channel equalization */
if (!intel_dp_set_link_train(intel_dp, if (!intel_dp_set_link_train(intel_dp,
training_pattern | training_pattern |