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[POWERPC] 83xx: Add MPC832x RDB board support.
Add support for the MPC8323E Reference Development Board (RDB). The board is a mini-ITX reference board with 64M DDR2, 16M flash, USB, PCI, 10/100 ethernet, serial, and phone ports. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Michael Barkowski
Kumar Gala
parent
1a4d9399a9
commit
23308c54d5
291
arch/powerpc/boot/dts/mpc832x_rdb.dts
Normal file
291
arch/powerpc/boot/dts/mpc832x_rdb.dts
Normal file
@ -0,0 +1,291 @@
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/*
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* MPC832x RDB Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8323ERDB";
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compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8323@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <4000>; // L1, 16K
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i-cache-size = <4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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32-bit;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 04000000>;
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};
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soc8323@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <200 100>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <e 8>;
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interrupt-parent = <&pic>;
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dfsrr;
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <9 8>;
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interrupt-parent = <&pic>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <a 8>;
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interrupt-parent = <&pic>;
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 7000>;
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interrupts = <b 8>;
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interrupt-parent = <&pic>;
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/* Rev. 2.2 */
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num-channels = <1>;
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channel-fifo-len = <18>;
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exec-units-mask = <0000004c>;
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descriptor-types-mask = <0122003f>;
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};
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pci@8500 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x10 AD16 (USB) */
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8000 0 0 1 &pic 11 8
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/* IDSEL 0x11 AD17 (Mini1)*/
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8800 0 0 1 &pic 12 8
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8800 0 0 2 &pic 13 8
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8800 0 0 3 &pic 14 8
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8800 0 0 4 &pic 30 8
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/* IDSEL 0x12 AD18 (PCI/Mini2) */
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9000 0 0 1 &pic 13 8
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9000 0 0 2 &pic 14 8
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9000 0 0 3 &pic 30 8
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9000 0 0 4 &pic 11 8>;
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interrupt-parent = <&pic>;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 10000000
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02000000 0 90000000 90000000 0 10000000
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01000000 0 d0000000 d0000000 0 04000000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <8500 100>;
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compatible = "83xx";
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device_type = "pci";
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};
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pic:pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <700 100>;
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built-in;
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device_type = "ipic";
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};
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par_io@1400 {
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reg = <1400 100>;
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device_type = "par_io";
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num-ports = <7>;
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ucc2pio:ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 4 3 0 2 0 /* MDIO */
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3 5 1 0 2 0 /* MDC */
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3 15 2 0 1 0 /* RX_CLK (CLK16) */
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3 17 2 0 1 0 /* TX_CLK (CLK3) */
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0 12 1 0 1 0 /* TxD0 */
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0 13 1 0 1 0 /* TxD1 */
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0 14 1 0 1 0 /* TxD2 */
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0 15 1 0 1 0 /* TxD3 */
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0 16 2 0 1 0 /* RxD0 */
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0 17 2 0 1 0 /* RxD1 */
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0 18 2 0 1 0 /* RxD2 */
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0 19 2 0 1 0 /* RxD3 */
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0 1a 2 0 1 0 /* RX_ER */
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0 1b 1 0 1 0 /* TX_ER */
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0 1c 2 0 1 0 /* RX_DV */
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0 1d 2 0 1 0 /* COL */
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0 1e 1 0 1 0 /* TX_EN */
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0 1f 2 0 1 0>; /* CRS */
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};
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ucc3pio:ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 d 2 0 1 0 /* RX_CLK (CLK9) */
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3 18 2 0 1 0 /* TX_CLK (CLK10) */
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1 0 1 0 1 0 /* TxD0 */
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1 1 1 0 1 0 /* TxD1 */
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1 2 1 0 1 0 /* TxD2 */
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1 3 1 0 1 0 /* TxD3 */
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1 4 2 0 1 0 /* RxD0 */
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1 5 2 0 1 0 /* RxD1 */
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1 6 2 0 1 0 /* RxD2 */
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1 7 2 0 1 0 /* RxD3 */
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1 8 2 0 1 0 /* RX_ER */
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1 9 1 0 1 0 /* TX_ER */
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1 a 2 0 1 0 /* RX_DV */
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1 b 2 0 1 0 /* COL */
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1 c 1 0 1 0 /* TX_EN */
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1 d 2 0 1 0>; /* CRS */
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};
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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model = "QE";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <BCD3D80>;
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muram@10000 {
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device_type = "muram";
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ranges = <0 00010000 00004000>;
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data-only@0 {
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reg = <0 4000>;
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};
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};
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spi@4c0 {
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device_type = "spi";
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compatible = "fsl_spi";
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reg = <4c0 40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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spi@500 {
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device_type = "spi";
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compatible = "fsl_spi";
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reg = <500 40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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device-id = <2>;
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reg = <3000 200>;
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interrupts = <21>;
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interrupt-parent = <&qeic>;
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mac-address = [ 00 04 9f ef 03 02 ];
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rx-clock = <20>;
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tx-clock = <13>;
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phy-handle = <&phy00>;
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pio-handle = <&ucc2pio>;
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};
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ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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device-id = <3>;
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reg = <2200 200>;
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interrupts = <22>;
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interrupt-parent = <&qeic>;
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mac-address = [ 00 04 9f ef 03 01 ];
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rx-clock = <19>;
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tx-clock = <1a>;
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phy-handle = <&phy04>;
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pio-handle = <&ucc3pio>;
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};
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mdio@3120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3120 18>;
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device_type = "mdio";
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compatible = "ucc_geth_phy";
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phy00:ethernet-phy@00 {
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interrupt-parent = <&pic>;
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interrupts = <0>;
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reg = <0>;
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device_type = "ethernet-phy";
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interface = <3>; //ENET_100_MII
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};
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phy04:ethernet-phy@04 {
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interrupt-parent = <&pic>;
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interrupts = <0>;
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reg = <4>;
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device_type = "ethernet-phy";
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interface = <3>;
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};
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};
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qeic:qeic@80 {
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interrupt-controller;
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device_type = "qeic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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built-in;
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big-endian;
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interrupts = <20 8 21 8>; //high:32 low:33
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interrupt-parent = <&pic>;
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};
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};
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};
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1292
arch/powerpc/configs/mpc832x_rdb_defconfig
Normal file
1292
arch/powerpc/configs/mpc832x_rdb_defconfig
Normal file
File diff suppressed because it is too large
Load Diff
@ -18,6 +18,13 @@ config MPC832x_MDS
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help
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This option enables support for the MPC832x MDS evaluation board.
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config MPC832x_RDB
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bool "Freescale MPC832x RDB"
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select DEFAULT_UIMAGE
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select QUICC_ENGINE
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help
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This option enables support for the MPC8323 RDB board.
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config MPC834x_MDS
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bool "Freescale MPC834x MDS"
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select DEFAULT_UIMAGE
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@ -57,7 +64,7 @@ config PPC_MPC832x
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bool
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select PPC_UDBG_16550
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select PPC_INDIRECT_PCI
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default y if MPC832x_MDS
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default y if MPC832x_MDS || MPC832x_RDB
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config MPC834x
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bool
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@ -4,6 +4,7 @@
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obj-y := misc.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_MPC8313_RDB) += mpc8313_rdb.o
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obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
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obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
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obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
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obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
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138
arch/powerpc/platforms/83xx/mpc832x_rdb.c
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138
arch/powerpc/platforms/83xx/mpc832x_rdb.c
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@ -0,0 +1,138 @@
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/*
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* arch/powerpc/platforms/83xx/mpc832x_rdb.c
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*
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* Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
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*
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* Description:
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* MPC832x RDB board specific routines.
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* This file is based on mpc832x_mds.c and mpc8313_rdb.c
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* Author: Michael Barkowski <michael.barkowski@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/pci.h>
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#include <asm/of_platform.h>
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#include <asm/time.h>
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#include <asm/ipic.h>
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#include <asm/udbg.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include "mpc83xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#ifndef CONFIG_PCI
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unsigned long isa_io_base = 0;
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unsigned long isa_mem_base = 0;
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#endif
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init mpc832x_rdb_setup_arch(void)
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{
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struct device_node *np;
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if (ppc_md.progress)
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ppc_md.progress("mpc832x_rdb_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
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add_bridge(np);
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ppc_md.pci_exclude_device = mpc83xx_exclude_device;
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#endif
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#ifdef CONFIG_QUICC_ENGINE
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qe_reset();
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if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
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par_io_init(np);
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of_node_put(np);
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for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
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par_io_of_config(np);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static struct of_device_id mpc832x_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{},
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};
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static int __init mpc832x_declare_of_platform_devices(void)
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{
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if (!machine_is(mpc832x_rdb))
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return 0;
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/* Publish the QE devices */
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of_platform_bus_probe(NULL, mpc832x_ids, NULL);
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return 0;
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}
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device_initcall(mpc832x_declare_of_platform_devices);
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void __init mpc832x_rdb_init_IRQ(void)
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{
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struct device_node *np;
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np = of_find_node_by_type(NULL, "ipic");
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if (!np)
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return;
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ipic_init(np, 0);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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ipic_set_default_priority();
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of_node_put(np);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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qe_ic_init(np, 0);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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}
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init mpc832x_rdb_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC832xRDB");
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}
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define_machine(mpc832x_rdb) {
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.name = "MPC832x RDB",
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.probe = mpc832x_rdb_probe,
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.setup_arch = mpc832x_rdb_setup_arch,
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.init_IRQ = mpc832x_rdb_init_IRQ,
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.get_irq = ipic_get_irq,
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.restart = mpc83xx_restart,
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.time_init = mpc83xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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