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nds32 patches for 5.5-rc1

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Here is the nds32 patchset based on 5.4-rc8
 Contained in here are
 1. code clean up
 2. add a nds32 maintainer
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Merge tag 'nds32-for-linus-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux

Pull nds32 updates from Greentime Hu:

 - code clean up

 - add a nds32 maintainer

* tag 'nds32-for-linus-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux:
  MAINTAINERS: add nds32 maintainer
  nds32: Move static keyword to the front of declaration
  nds32: Fix typo in Kconfig.cpu
  nds32: remove unneeded clean-files for DTB
This commit is contained in:
Linus Torvalds 2019-11-30 14:28:11 -08:00
commit 2309d07682
4 changed files with 6 additions and 7 deletions
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1
MAINTAINERS
View File

@ -1049,6 +1049,7 @@ F: drivers/clk/analogbits/*
F: include/linux/clk/analogbits*
ANDES ARCHITECTURE
M: Nick Hu <nickhu@andestech.com>
M: Greentime Hu <green.hu@gmail.com>
M: Vincent Chen <deanbo422@gmail.com>
T: git https://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux.git

8
arch/nds32/Kconfig.cpu
View File

@ -13,7 +13,7 @@ config FPU
default n
help
If FPU ISA is used in user space, this configuration shall be Y to
enable required support in kerenl such as fpu context switch and
enable required support in kernel such as fpu context switch and
fpu exception handler.
If no FPU ISA is used in user space, say N.
@ -27,7 +27,7 @@ config LAZY_FPU
enhance system performance by reducing the context switch
frequency of the FPU register.
For nomal case, say Y.
For normal case, say Y.
config SUPPORT_DENORMAL_ARITHMETIC
bool "Denormal arithmetic support"
@ -36,7 +36,7 @@ config SUPPORT_DENORMAL_ARITHMETIC
help
Say Y here to enable arithmetic of denormalized number. Enabling
this feature can enhance the precision for tininess number.
However, performance loss in float pointe calculations is
However, performance loss in float point calculations is
possibly significant due to additional FPU exception.
If the calculated tolerance for tininess number is not critical,
@ -73,7 +73,7 @@ choice
the cache aliasing issue. The rest cpus(N13, N10 and D10) are
implemented as VIPT data cache. It may cause the cache aliasing issue
if its cache way size is larger than page size. You can specify the
CPU type direcly or choose CPU_V3 if unsure.
CPU type directly or choose CPU_V3 if unsure.
A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
A kernel built for N15 is able to run on N15 or D15.

2
arch/nds32/boot/dts/Makefile
View File

@ -5,5 +5,3 @@ else
BUILTIN_DTB :=
endif
obj-$(CONFIG_OF) += $(BUILTIN_DTB)
clean-files := *.dtb *.dtb.S

2
arch/nds32/kernel/perf_event_cpu.c
View File

@ -1119,7 +1119,7 @@ static void cpu_pmu_init(struct nds32_pmu *cpu_pmu)
on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
}
const static struct of_device_id cpu_pmu_of_device_ids[] = {
static const struct of_device_id cpu_pmu_of_device_ids[] = {
{.compatible = "andestech,nds32v3-pmu",
.data = device_pmu_init},
{},