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[PATCH] Change maxaligned_in_smp alignemnt macros to internodealigned_in_smp macros

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____cacheline_maxaligned_in_smp is currently used to align critical structures
and avoid false sharing.  It uses per-arch L1_CACHE_SHIFT_MAX and people find
L1_CACHE_SHIFT_MAX useless.

However, we have been using ____cacheline_maxaligned_in_smp to align
structures on the internode cacheline size.  As per Andi's suggestion,
following patch kills ____cacheline_maxaligned_in_smp and introduces
INTERNODE_CACHE_SHIFT, which defaults to L1_CACHE_SHIFT for all arches.
Arches needing L3/Internode cacheline alignment can define
INTERNODE_CACHE_SHIFT in the arch asm/cache.h.  Patch replaces
____cacheline_maxaligned_in_smp with ____cacheline_internodealigned_in_smp

With this patch, L1_CACHE_SHIFT_MAX can be killed

Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org>
Signed-off-by: Shai Fultheim <shai@scalex86.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Ravikiran G Thirumalai 2006-01-08 01:01:27 -08:00 committed by Linus Torvalds
parent 6d524aed1f
commit 22fc6eccbf
9 changed files with 24 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/i386/kernel/init_task.c
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@ -42,5 +42,5 @@ EXPORT_SYMBOL(init_task);
* per-CPU TSS segments. Threads are completely 'soft' on Linux,
* no more per-task TSS's.
*/
DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_maxaligned_in_smp = INIT_TSS;
DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;

2
arch/i386/kernel/irq.c
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@ -19,7 +19,7 @@
#include <linux/cpu.h>
#include <linux/delay.h>
DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_maxaligned_in_smp;
DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
EXPORT_PER_CPU_SYMBOL(irq_stat);
#ifndef CONFIG_X86_LOCAL_APIC

2
arch/x86_64/kernel/init_task.c
View File

@ -44,6 +44,6 @@ EXPORT_SYMBOL(init_task);
* section. Since TSS's are completely CPU-local, we want them
* on exact cacheline boundaries, to eliminate cacheline ping-pong.
*/
DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_maxaligned_in_smp = INIT_TSS;
DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;
#define ALIGN_TO_4K __attribute__((section(".data.init_task")))

17
include/linux/cache.h
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@ -45,12 +45,21 @@
#endif /* CONFIG_SMP */
#endif
#if !defined(____cacheline_maxaligned_in_smp)
/*
* The maximum alignment needed for some critical structures
* These could be inter-node cacheline sizes/L3 cacheline
* size etc. Define this in asm/cache.h for your arch
*/
#ifndef INTERNODE_CACHE_SHIFT
#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
#endif
#if !defined(____cacheline_internodealigned_in_smp)
#if defined(CONFIG_SMP)
#define ____cacheline_maxaligned_in_smp \
__attribute__((__aligned__(1 << (L1_CACHE_SHIFT_MAX))))
#define ____cacheline_internodealigned_in_smp \
__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))
#else
#define ____cacheline_maxaligned_in_smp
#define ____cacheline_internodealigned_in_smp
#endif
#endif

2
include/linux/ide.h
View File

@ -801,7 +801,7 @@ typedef struct hwif_s {
unsigned dma;
void (*led_act)(void *data, int rw);
} ____cacheline_maxaligned_in_smp ide_hwif_t;
} ____cacheline_internodealigned_in_smp ide_hwif_t;
/*
* internal ide interrupt handler type

4
include/linux/mmzone.h
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@ -38,7 +38,7 @@ struct pglist_data;
#if defined(CONFIG_SMP)
struct zone_padding {
char x[0];
} ____cacheline_maxaligned_in_smp;
} ____cacheline_internodealigned_in_smp;
#define ZONE_PADDING(name) struct zone_padding name;
#else
#define ZONE_PADDING(name)
@ -233,7 +233,7 @@ struct zone {
* rarely used fields:
*/
char *name;
} ____cacheline_maxaligned_in_smp;
} ____cacheline_internodealigned_in_smp;
/*

2
include/linux/rcupdate.h
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@ -65,7 +65,7 @@ struct rcu_ctrlblk {
long cur; /* Current batch number. */
long completed; /* Number of the last completed batch */
int next_pending; /* Is the next batch already waiting? */
} ____cacheline_maxaligned_in_smp;
} ____cacheline_internodealigned_in_smp;
/* Is batch a before batch b ? */
static inline int rcu_batch_before(long a, long b)

4
kernel/rcupdate.c
View File

@ -61,9 +61,9 @@ struct rcu_state {
/* for current batch to proceed. */
};
static struct rcu_state rcu_state ____cacheline_maxaligned_in_smp =
static struct rcu_state rcu_state ____cacheline_internodealigned_in_smp =
{.lock = SPIN_LOCK_UNLOCKED, .cpumask = CPU_MASK_NONE };
static struct rcu_state rcu_bh_state ____cacheline_maxaligned_in_smp =
static struct rcu_state rcu_bh_state ____cacheline_internodealigned_in_smp =
{.lock = SPIN_LOCK_UNLOCKED, .cpumask = CPU_MASK_NONE };
DEFINE_PER_CPU(struct rcu_data, rcu_data) = { 0L };

4
mm/sparse.c
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@ -18,10 +18,10 @@
*/
#ifdef CONFIG_SPARSEMEM_EXTREME
struct mem_section *mem_section[NR_SECTION_ROOTS]
____cacheline_maxaligned_in_smp;
____cacheline_internodealigned_in_smp;
#else
struct mem_section mem_section[NR_SECTION_ROOTS][SECTIONS_PER_ROOT]
____cacheline_maxaligned_in_smp;
____cacheline_internodealigned_in_smp;
#endif
EXPORT_SYMBOL(mem_section);