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clk: rockchip: mark some special clk as critical on rk3368
The jtag clk no driver to handle them. But this clk need enable,so make it as critical. The ddrphy/ddrupctl clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
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GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
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RK3368_CLKGATE_CON(7), 5, GFLAGS),
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GATE(0, "jtag", "ext_jtag", 0,
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GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
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RK3368_CLKGATE_CON(7), 0, GFLAGS),
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COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
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@ -861,6 +861,9 @@ static const char *const rk3368_critical_clocks[] __initconst = {
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"pclk_pd_alive",
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"pclk_peri",
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"hclk_peri",
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"pclk_ddrphy",
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"pclk_ddrupctl",
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"pmu_hclk_otg0",
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};
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static void __init rk3368_clk_init(struct device_node *np)
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