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phy: cadence-torrent: Refactor code for reusability
Add a separate function to set different power state values. Use uniform polling timeout value. Also check return values of functions for proper error handling. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Swapnil Jakhade
Kishon Vijay Abraham I
parent
f61b3aed20
commit
21c79146a1
@ -22,7 +22,7 @@
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#define MAX_NUM_LANES 4
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#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
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#define POLL_TIMEOUT_US 2000
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#define POLL_TIMEOUT_US 5000
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#define LANE_MASK 0x7
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/*
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@ -39,6 +39,7 @@
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#define PHY_POWER_STATE_LN_1 0x0008
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#define PHY_POWER_STATE_LN_2 0x0010
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#define PHY_POWER_STATE_LN_3 0x0018
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#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
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#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
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#define PHY_PMA_CMN_READY 0x34
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#define PHY_PMA_XCVR_TX_VMARGIN 0x38
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@ -109,10 +110,17 @@ struct cdns_torrent_phy {
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struct device *dev;
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};
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enum phy_powerstate {
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POWERSTATE_A0 = 0,
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/* Powerstate A1 is unused */
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POWERSTATE_A2 = 2,
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POWERSTATE_A3 = 3,
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};
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static int cdns_torrent_dp_init(struct phy *phy);
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static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
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static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
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static
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void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
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int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
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static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy);
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static
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void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
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@ -158,9 +166,46 @@ static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
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readl_poll_timeout((cdns_phy)->base + (offset), \
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val, cond, delay_us, timeout_us)
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/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
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static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
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u32 num_lanes)
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{
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u32 pwr_state = cdns_torrent_dp_read(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ);
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u32 pll_clk_en = cdns_torrent_dp_read(cdns_phy,
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PHY_PMA_XCVR_PLLCLK_EN);
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/* Lane 0 is always enabled. */
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pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
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PHY_POWER_STATE_LN_0);
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pll_clk_en &= ~0x01U;
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if (num_lanes > 1) {
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/* lane 1 */
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pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
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PHY_POWER_STATE_LN_1);
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pll_clk_en &= ~(0x01U << 1);
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}
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if (num_lanes > 2) {
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/* lanes 2 and 3 */
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pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
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PHY_POWER_STATE_LN_2);
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pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
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PHY_POWER_STATE_LN_3);
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pll_clk_en &= ~(0x01U << 2);
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pll_clk_en &= ~(0x01U << 3);
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}
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cdns_torrent_dp_write(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
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}
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static int cdns_torrent_dp_init(struct phy *phy)
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{
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unsigned char lane_bits;
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int ret;
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struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
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@ -173,40 +218,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
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* Set lines power state to A0
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* Set lines pll clk enable to 0
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*/
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cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_0, 6, 0x0000);
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if (cdns_phy->num_lanes >= 2) {
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_1, 6, 0x0000);
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if (cdns_phy->num_lanes == 4) {
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_2, 6, 0);
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ,
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PHY_POWER_STATE_LN_3, 6, 0);
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}
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}
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cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
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0, 1, 0x0000);
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if (cdns_phy->num_lanes >= 2) {
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cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
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1, 1, 0x0000);
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if (cdns_phy->num_lanes == 4) {
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_PLLCLK_EN,
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2, 1, 0x0000);
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cdns_dp_phy_write_field(cdns_phy,
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PHY_PMA_XCVR_PLLCLK_EN,
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3, 1, 0x0000);
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}
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}
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cdns_torrent_dp_set_a0_pll(cdns_phy, cdns_phy->num_lanes);
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/*
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* release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
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@ -225,23 +237,31 @@ static int cdns_torrent_dp_init(struct phy *phy)
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/* take out of reset */
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cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
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cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
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cdns_torrent_dp_run(cdns_phy);
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ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
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if (ret)
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return ret;
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return 0;
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ret = cdns_torrent_dp_run(cdns_phy);
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return ret;
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}
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static
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void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
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int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
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{
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unsigned int reg;
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int ret;
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
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reg, reg & 1, 0, 500);
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if (ret == -ETIMEDOUT)
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reg, reg & 1, 0,
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POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT) {
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dev_err(cdns_phy->dev,
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"timeout waiting for PMA common ready\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy)
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@ -397,12 +417,73 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
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(XCVR_DIAG_HSCLK_SEL | lane_bits), 0x0000);
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}
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static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
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static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
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u32 num_lanes,
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enum phy_powerstate powerstate)
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{
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/* Register value for power state for a single byte. */
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u32 value_part;
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u32 value;
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u32 mask;
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u32 read_val;
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u32 ret;
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switch (powerstate) {
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case (POWERSTATE_A0):
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value_part = 0x01U;
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break;
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case (POWERSTATE_A2):
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value_part = 0x04U;
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break;
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default:
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/* Powerstate A3 */
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value_part = 0x08U;
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break;
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}
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/* Select values of registers and mask, depending on enabled
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* lane count.
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*/
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switch (num_lanes) {
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/* lane 0 */
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case (1):
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value = value_part;
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mask = 0x0000003FU;
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break;
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/* lanes 0-1 */
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case (2):
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value = (value_part
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| (value_part << 8));
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mask = 0x00003F3FU;
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break;
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/* lanes 0-3, all */
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default:
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value = (value_part
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| (value_part << 8)
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| (value_part << 16)
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| (value_part << 24));
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mask = 0x3F3F3F3FU;
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break;
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}
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/* Set power state A<n>. */
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, value);
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/* Wait, until PHY acknowledges power state completion. */
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_ACK,
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read_val,
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(read_val & mask) == value, 0,
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POLL_TIMEOUT_US);
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cdns_torrent_dp_write(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
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ndelay(100);
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return ret;
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}
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static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
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{
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unsigned int read_val;
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u32 write_val1 = 0;
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u32 write_val2 = 0;
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u32 mask = 0;
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int ret;
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/*
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@ -413,60 +494,23 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
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PHY_PMA_XCVR_PLLCLK_EN_ACK,
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read_val, read_val & 1, 0,
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POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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if (ret == -ETIMEDOUT) {
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dev_err(cdns_phy->dev,
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"timeout waiting for link PLL clock enable ack\n");
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ndelay(100);
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switch (cdns_phy->num_lanes) {
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case 1: /* lane 0 */
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write_val1 = 0x00000004;
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write_val2 = 0x00000001;
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mask = 0x0000003f;
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break;
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case 2: /* lane 0-1 */
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write_val1 = 0x00000404;
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write_val2 = 0x00000101;
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mask = 0x00003f3f;
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break;
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case 4: /* lane 0-3 */
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write_val1 = 0x04040404;
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write_val2 = 0x01010101;
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mask = 0x3f3f3f3f;
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break;
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return ret;
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}
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cdns_torrent_dp_write(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ, write_val1);
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_ACK,
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read_val,
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(read_val & mask) == write_val1,
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0, POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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"timeout waiting for link power state ack\n");
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
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ndelay(100);
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cdns_torrent_dp_write(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_REQ, write_val2);
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ret = cdns_torrent_dp_set_power_state(cdns_phy, cdns_phy->num_lanes,
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POWERSTATE_A2);
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if (ret)
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return ret;
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ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
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PHY_PMA_XCVR_POWER_STATE_ACK,
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read_val,
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(read_val & mask) == write_val2,
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0, POLL_TIMEOUT_US);
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if (ret == -ETIMEDOUT)
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dev_err(cdns_phy->dev,
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"timeout waiting for link power state ack\n");
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ret = cdns_torrent_dp_set_power_state(cdns_phy, cdns_phy->num_lanes,
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POWERSTATE_A0);
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cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
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ndelay(100);
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return ret;
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}
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static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
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