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clk: meson: Fix GXL HDMI PLL fractional bits width

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The GXL Documentation specifies 12 bits for the Fractional bit field,
bit the last bits have a different purpose that we cannot handle right
now, so update the bitwidth to have correct fractional calculations.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added comment on GXL HHI_HDMI_PLL_CNTL register shift]
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20181121111922.1277-1-narmstrong@baylibre.com
This commit is contained in:
Neil Armstrong 2018-11-21 12:19:22 +01:00
parent a7d19b05ce
commit 21310c39ec
1 changed files with 7 additions and 1 deletions
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8
drivers/clk/meson/gxbb.c
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@ -216,10 +216,16 @@ static struct clk_regmap gxl_hdmi_pll_dco = {
.shift = 9,
.width = 5,
},
/*
* On gxl, there is a register shift due to
* HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
* so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
* instead which is defined at the same offset.
*/
.frac = {
.reg_off = HHI_HDMI_PLL_CNTL2,
.shift = 0,
.width = 12,
.width = 10,
},
.l = {
.reg_off = HHI_HDMI_PLL_CNTL,