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Merge branch '4.0-rc1-prcm-cleanup-v6' of https://github.com/t-kristo/linux-pm into omap-for-v4.1/prcm-cleanup

Browse Source 
Conflicts:
	arch/arm/boot/dts/dra7.dtsi
This commit is contained in:
Tony Lindgren 2015-04-01 12:24:29 -07:00
commit 2129536836
66 changed files with 1659 additions and 847 deletions
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79
Documentation/devicetree/bindings/arm/omap/ctrl.txt Normal file
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@ -0,0 +1,79 @@
OMAP Control Module bindings
Control Module contains miscellaneous features under it based on SoC type.
Pincontrol is one common feature, and it has a specialized support
described in [1]. Typically some clock nodes are also under control module.
Syscon is used to share register level access to drivers external to
control module driver itself.
See [2] for documentation about clock/clockdomain nodes.
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
[2] Documentation/devicetree/bindings/clock/ti/*
Required properties:
- compatible: Must be one of:
"ti,am3-scm"
"ti,am4-scm"
"ti,dm814-scrm"
"ti,dm816-scrm"
"ti,omap2-scm"
"ti,omap3-scm"
"ti,omap4-scm-core"
"ti,omap4-scm-padconf-core"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)
Optional properties:
- clocks: clocks for this module
- clockdomains: clockdomains for this module
Examples:
scm: scm@2000 {
compatible = "ti,omap3-scm", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
omap3_pmx_core: pinmux@30 {
compatible = "ti,omap3-padconf",
"pinctrl-single";
reg = <0x30 0x230>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x330>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
}
&scm_clocks {
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
};
};

26
Documentation/devicetree/bindings/arm/omap/l4.txt Normal file
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@ -0,0 +1,26 @@
L4 interconnect bindings
These bindings describe the OMAP SoCs L4 interconnect bus.
Required properties:
- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
l4: l4@48000000 {
compatible "ti,omap2-l4", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
};

6
Documentation/devicetree/bindings/arm/omap/prcm.txt
View File

@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible: Must be one of:
"ti,am3-prcm"
"ti,am3-scrm"
"ti,am4-prcm"
"ti,am4-scrm"
"ti,omap2-prcm"
"ti,omap2-scrm"
"ti,omap3-prm"
"ti,omap3-cm"
"ti,omap3-scrm"
"ti,omap4-cm1"
"ti,omap4-prm"
"ti,omap4-cm2"
@ -29,6 +25,8 @@ Required properties:
"ti,dra7-prm"
"ti,dra7-cm-core-aon"
"ti,dra7-cm-core"
"ti,dm814-prcm"
"ti,dm816-prcm"
- reg: Contains PRCM module register address range
(base address and length)
- clocks: clocks for this module

2
arch/arm/boot/dts/am33xx-clocks.dtsi
View File

@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";

93
arch/arm/boot/dts/am33xx.dtsi
View File

@ -83,20 +83,6 @@
};
};
am33xx_control_module: control_module@4a002000 {
compatible = "syscon";
reg = <0x44e10000 0x7fc>;
};
am33xx_pinmux: pinmux@44e10800 {
compatible = "pinctrl-single";
reg = <0x44e10800 0x0238>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
@ -111,35 +97,56 @@
ranges;
ti,hwmods = "l3_main";
prcm: prcm@44e00000 {
compatible = "ti,am3-prcm";
reg = <0x44e00000 0x4000>;
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am3-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
prcm_clocks: clocks {
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
reg = <0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@210000 {
compatible = "ti,am3-scm", "simple-bus";
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@44e10000 {
compatible = "ti,am3-scrm";
reg = <0x44e10000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
cm: syscon@44e10000 {
compatible = "ti,am33xx-controlmodule", "syscon";
reg = <0x44e10000 0x800>;
};
intc: interrupt-controller@48200000 {
@ -350,7 +357,7 @@
reg = <0x481cc000 0x2000>;
clocks = <&dcan0_fck>;
clock-names = "fck";
syscon-raminit = <&am33xx_control_module 0x644 0>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <52>;
status = "disabled";
};
@ -361,7 +368,7 @@
reg = <0x481d0000 0x2000>;
clocks = <&dcan1_fck>;
clock-names = "fck";
syscon-raminit = <&am33xx_control_module 0x644 1>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <55>;
status = "disabled";
};
@ -720,7 +727,7 @@
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&cm>;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@4a101000 {

2
arch/arm/boot/dts/am3517.dtsi
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@ -31,7 +31,7 @@
status = "disabled";
reg = <0x5c000000 0x30000>;
interrupts = <67 68 69 70>;
syscon = <&omap3_scm_general>;
syscon = <&scm_conf>;
ti,davinci-ctrl-reg-offset = <0x10000>;
ti,davinci-ctrl-mod-reg-offset = <0>;
ti,davinci-ctrl-ram-offset = <0x20000>;

2
arch/arm/boot/dts/am35xx-clocks.dtsi
View File

@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
emac_ick: emac_ick {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";

83
arch/arm/boot/dts/am4372.dtsi
View File

@ -57,22 +57,6 @@
cache-level = <2>;
};
am43xx_control_module: control_module@4a002000 {
compatible = "syscon";
reg = <0x44e10000 0x7f4>;
};
am43xx_pinmux: pinmux@44e10800 {
compatible = "ti,am437-padconf", "pinctrl-single";
reg = <0x44e10800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
ocp {
compatible = "ti,am4372-l3-noc", "simple-bus";
#address-cells = <1>;
@ -84,29 +68,58 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prcm: prcm@44df0000 {
compatible = "ti,am4-prcm";
reg = <0x44df0000 0x11000>;
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
prcm_clocks: clocks {
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
reg = <0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@210000 {
compatible = "ti,am4-scm", "simple-bus";
reg = <0x210000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
};
#size-cells = <1>;
ranges = <0 0x210000 0x4000>;
prcm_clockdomains: clockdomains {
};
};
am43xx_pinmux: pinmux@800 {
compatible = "ti,am437-padconf",
"pinctrl-single";
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
scrm: scrm@44e10000 {
compatible = "ti,am4-scrm";
reg = <0x44e10000 0x2000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scrm_clockdomains: clockdomains {
scm_clockdomains: clockdomains {
};
};
};
@ -933,7 +946,7 @@
clocks = <&dcan0_fck>;
clock-names = "fck";
reg = <0x481cc000 0x2000>;
syscon-raminit = <&am43xx_control_module 0x644 0>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -944,7 +957,7 @@
clocks = <&dcan1_fck>;
clock-names = "fck";
reg = <0x481d0000 0x2000>;
syscon-raminit = <&am43xx_control_module 0x644 1>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

84
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -69,7 +69,48 @@
};
};
am43xx_pinmux: pinmux@44e10800 {
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
linux,keymap = <0x00000201 /* P1 */
0x01000204 /* P4 */
0x02000207 /* P7 */
0x0300020a /* NUMERIC_STAR */
0x00010202 /* P2 */
0x01010205 /* P5 */
0x02010208 /* P8 */
0x03010200 /* P0 */
0x00020203 /* P3 */
0x01020206 /* P6 */
0x02020209 /* P9 */
0x0302020b /* NUMERIC_POUND */
0x00030067 /* UP */
0x0103006a /* RIGHT */
0x0203006c /* DOWN */
0x03030069>; /* LEFT */
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
};
&am43xx_pinmux {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
@ -279,47 +320,6 @@
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
linux,keymap = <0x00000201 /* P1 */
0x01000204 /* P4 */
0x02000207 /* P7 */
0x0300020a /* NUMERIC_STAR */
0x00010202 /* P2 */
0x01010205 /* P5 */
0x02010208 /* P8 */
0x03010200 /* P0 */
0x00020203 /* P3 */
0x01020206 /* P6 */
0x02020209 /* P9 */
0x0302020b /* NUMERIC_POUND */
0x00030067 /* UP */
0x0103006a /* RIGHT */
0x0203006c /* DOWN */
0x03030069>; /* LEFT */
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
};
&mmc1 {

2
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";

156
arch/arm/boot/dts/dra7.dtsi
View File

@ -94,17 +94,101 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,dra7-prm";
reg = <0x4ae06000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
l4_cfg: l4@4a000000 {
compatible = "ti,dra7-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x22c000>;
prm_clocks: clocks {
scm: scm@2000 {
compatible = "ti,dra7-scm-core", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
dra7_pmx_core: pinmux@1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
reg = <0x1400 0x0464>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
};
prm_clockdomains: clockdomains {
cm_core_aon: cm_core_aon@5000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@8000 {
compatible = "ti,dra7-cm-core";
reg = <0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
};
l4_wkup: l4@4ae00000 {
compatible = "ti,dra7-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4ae00000 0x3f000>;
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x40>;
ti,hwmods = "counter_32k";
};
prm: prm@6000 {
compatible = "ti,dra7-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
};
@ -189,38 +273,6 @@
#thermal-sensor-cells = <1>;
};
cm_core_aon: cm_core_aon@4a005000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x4a005000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@4a008000 {
compatible = "ti,dra7-cm-core";
reg = <0x4a008000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
ti,hwmods = "counter_32k";
};
dra7_ctrl_core: ctrl_core@4a002000 {
compatible = "syscon";
reg = <0x4a002000 0x6d0>;
@ -231,28 +283,6 @@
reg = <0x4a002e00 0x7c>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0 0x4>;
syscon = <&dra7_ctrl_general>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
dra7_pmx_core: pinmux@4a003400 {
compatible = "ti,dra7-padconf", "pinctrl-single";
reg = <0x4a003400 0x0464>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
@ -1422,7 +1452,7 @@
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan1";
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&dra7_ctrl_core 0x558 0>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>;
status = "disabled";
@ -1432,7 +1462,7 @@
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan2";
reg = <0x48480000 0x2000>;
syscon-raminit = <&dra7_ctrl_core 0x558 1>;
syscon-raminit = <&scm_conf 0x558 1>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clkin1>;
status = "disabled";

94
arch/arm/boot/dts/omap2420.dtsi
View File

@ -14,45 +14,63 @@
compatible = "ti,omap2420", "ti,omap2";
ocp {
prcm: prcm@48008000 {
compatible = "ti,omap2-prcm";
reg = <0x48008000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@48000000 {
compatible = "ti,omap2-scrm";
reg = <0x48000000 0x1000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48004000 {
compatible = "ti,omap-counter32k";
reg = <0x48004000 0x20>;
ti,hwmods = "counter_32k";
};
omap2420_pmx: pinmux@48000030 {
compatible = "ti,omap2420-padconf", "pinctrl-single";
reg = <0x48000030 0x0113>;
l4: l4@48000000 {
compatible = "ti,omap2-l4", "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
prcm: prcm@8000 {
compatible = "ti,omap2-prcm";
reg = <0x8000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@0 {
compatible = "ti,omap2-scm", "simple-bus";
reg = <0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x1000>;
omap2420_pmx: pinmux@30 {
compatible = "ti,omap2420-padconf",
"pinctrl-single";
reg = <0x30 0x0113>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x100>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
};
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
};
};
gpio1: gpio@48018000 {

8
arch/arm/boot/dts/omap2430-clocks.dtsi
View File

@ -8,12 +8,12 @@
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
mcbsp3_mux_fck: mcbsp3_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
reg = <0x02e8>;
reg = <0x78>;
};
mcbsp3_fck: mcbsp3_fck {
@ -27,7 +27,7 @@
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x02e8>;
reg = <0x78>;
};
mcbsp4_fck: mcbsp4_fck {
@ -41,7 +41,7 @@
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02e8>;
reg = <0x78>;
};
mcbsp5_fck: mcbsp5_fck {

115
arch/arm/boot/dts/omap2430.dtsi
View File

@ -14,60 +14,73 @@
compatible = "ti,omap2430", "ti,omap2";
ocp {
prcm: prcm@49006000 {
compatible = "ti,omap2-prcm";
reg = <0x49006000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@49002000 {
compatible = "ti,omap2-scrm";
reg = <0x49002000 0x1000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@49020000 {
compatible = "ti,omap-counter32k";
reg = <0x49020000 0x20>;
ti,hwmods = "counter_32k";
};
omap2430_pmx: pinmux@49002030 {
compatible = "ti,omap2430-padconf", "pinctrl-single";
reg = <0x49002030 0x0154>;
l4_wkup: l4_wkup@49000000 {
compatible = "ti,omap2-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
#size-cells = <1>;
ranges = <0 0x49000000 0x31000>;
omap2_scm_general: tisyscon@49002270 {
compatible = "syscon";
reg = <0x49002270 0x240>;
};
prcm: prcm@6000 {
compatible = "ti,omap2-prcm";
reg = <0x6000 0x1000>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&omap2_scm_general>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm_clockdomains: clockdomains {
};
};
scm: scm@2000 {
compatible = "ti,omap2-scm", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
omap2430_pmx: pinmux@30 {
compatible = "ti,omap2430-padconf",
"pinctrl-single";
reg = <0x30 0x0154>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x240>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
scm_clockdomains: clockdomains {
};
};
counter32k: counter@20000 {
compatible = "ti,omap-counter32k";
reg = <0x20000 0x20>;
ti,hwmods = "counter_32k";
};
};

6
arch/arm/boot/dts/omap24xx-clocks.dtsi
View File

@ -7,13 +7,13 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
mcbsp1_mux_fck: mcbsp1_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x0274>;
reg = <0x4>;
};
mcbsp1_fck: mcbsp1_fck {
@ -27,7 +27,7 @@
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <6>;
reg = <0x0274>;
reg = <0x4>;
};
mcbsp2_fck: mcbsp2_fck {

96
arch/arm/boot/dts/omap3.dtsi
View File

@ -87,6 +87,60 @@
ranges;
ti,hwmods = "l3_main";
l4_core: l4@48000000 {
compatible = "ti,omap3-l4-core", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x1000000>;
scm: scm@2000 {
compatible = "ti,omap3-scm", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
omap3_pmx_core: pinmux@30 {
compatible = "ti,omap3-padconf",
"pinctrl-single";
reg = <0x30 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x330>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
omap3_pmx_wkup: pinmux@a00 {
compatible = "ti,omap3-padconf",
"pinctrl-single";
reg = <0xa00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
};
};
aes: aes@480c5000 {
compatible = "ti,omap3-aes";
ti,hwmods = "aes";
@ -121,19 +175,6 @@
};
};
scrm: scrm@48002000 {
compatible = "ti,omap3-scrm";
reg = <0x48002000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
@ -159,37 +200,10 @@
#dma-requests = <96>;
};
omap3_pmx_core: pinmux@48002030 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002030 0x0238>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
omap3_pmx_wkup: pinmux@48002a00 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002a00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
omap3_scm_general: tisyscon@48002270 {
compatible = "syscon";
reg = <0x48002270 0x2f0>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&omap3_scm_general>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;

13
arch/arm/boot/dts/omap3xxx-clocks.dtsi
View File

@ -79,13 +79,14 @@
clock-div = <1>;
};
};
&scrm_clocks {
&scm_clocks {
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
reg = <0x68>;
};
mcbsp5_fck: mcbsp5_fck {
@ -99,7 +100,7 @@
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x0274>;
reg = <0x04>;
};
mcbsp1_fck: mcbsp1_fck {
@ -113,7 +114,7 @@
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <6>;
reg = <0x0274>;
reg = <0x04>;
};
mcbsp2_fck: mcbsp2_fck {
@ -126,7 +127,7 @@
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
reg = <0x02d8>;
reg = <0x68>;
};
mcbsp3_fck: mcbsp3_fck {
@ -140,7 +141,7 @@
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x02d8>;
reg = <0x68>;
};
mcbsp4_fck: mcbsp4_fck {

222
arch/arm/boot/dts/omap4.dtsi
View File

@ -114,99 +114,141 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
cm1: cm1@4a004000 {
compatible = "ti,omap4-cm1";
reg = <0x4a004000 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm1_clockdomains: clockdomains {
};
};
prm: prm@4a306000 {
compatible = "ti,omap4-prm";
reg = <0x4a306000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm2: cm2@4a008000 {
compatible = "ti,omap4-cm2";
reg = <0x4a008000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm2_clockdomains: clockdomains {
};
};
scrm: scrm@4a30a000 {
compatible = "ti,omap4-scrm";
reg = <0x4a30a000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@4a304000 {
compatible = "ti,omap-counter32k";
reg = <0x4a304000 0x20>;
ti,hwmods = "counter_32k";
};
omap4_pmx_core: pinmux@4a100040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a100040 0x0196>;
l4_cfg: l4@4a000000 {
compatible = "ti,omap4-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_pmx_wkup: pinmux@4a31e040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a31e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
#size-cells = <1>;
ranges = <0 0x4a000000 0x1000000>;
omap4_padconf_global: tisyscon@4a1005a0 {
compatible = "syscon";
reg = <0x4a1005a0 0x170>;
};
cm1: cm1@4000 {
compatible = "ti,omap4-cm1";
reg = <0x4000 0x2000>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {
regulator-name = "pbias_mmc_omap4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
cm1_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm1_clockdomains: clockdomains {
};
};
cm2: cm2@8000 {
compatible = "ti,omap4-cm2";
reg = <0x8000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm2_clockdomains: clockdomains {
};
};
omap4_scm_core: scm@2000 {
compatible = "ti,omap4-scm-core", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
};
omap4_padconf_core: scm@100000 {
compatible = "ti,omap4-scm-padconf-core",
"simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x100000 0x1000>;
omap4_pmx_core: pinmux@40 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x40 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_padconf_global: omap4_padconf_global@5a0 {
compatible = "syscon";
reg = <0x5a0 0x170>;
#address-cells = <1>;
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {
regulator-name = "pbias_mmc_omap4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
};
l4_wkup: l4@300000 {
compatible = "ti,omap4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300000 0x40000>;
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
};
prm: prm@6000 {
compatible = "ti,omap4-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
scrm: scrm@a000 {
compatible = "ti,omap4-scrm";
reg = <0xa000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
omap4_pmx_wkup: pinmux@1e040 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x1e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
};
};

218
arch/arm/boot/dts/omap5.dtsi
View File

@ -129,99 +129,141 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,omap5-prm";
reg = <0x4ae06000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm_core_aon: cm_core_aon@4a004000 {
compatible = "ti,omap5-cm-core-aon";
reg = <0x4a004000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
scrm: scrm@4ae0a000 {
compatible = "ti,omap5-scrm";
reg = <0x4ae0a000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
cm_core: cm_core@4a008000 {
compatible = "ti,omap5-cm-core";
reg = <0x4a008000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
ti,hwmods = "counter_32k";
};
omap5_pmx_core: pinmux@4a002840 {
compatible = "ti,omap5-padconf", "pinctrl-single";
reg = <0x4a002840 0x01b6>;
l4_cfg: l4@4a000000 {
compatible = "ti,omap5-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x22a000>;
scm_core: scm@2000 {
compatible = "ti,omap5-scm-core", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x800>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
};
scm_padconf_core: scm@2800 {
compatible = "ti,omap5-scm-padconf-core",
"simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x800>;
omap5_pmx_core: pinmux@40 {
compatible = "ti,omap5-padconf",
"pinctrl-single";
reg = <0x40 0x01b6>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap5_padconf_global: omap5_padconf_global@5a0 {
compatible = "syscon";
reg = <0x5a0 0xec>;
#address-cells = <1>;
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
};
cm_core_aon: cm_core_aon@4000 {
compatible = "ti,omap5-cm-core-aon";
reg = <0x4000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@8000 {
compatible = "ti,omap5-cm-core";
reg = <0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
};
omap5_pmx_wkup: pinmux@4ae0c840 {
compatible = "ti,omap5-padconf", "pinctrl-single";
reg = <0x4ae0c840 0x0038>;
l4_wkup: l4@4ae00000 {
compatible = "ti,omap5-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
#size-cells = <1>;
ranges = <0 0x4ae00000 0x2b000>;
omap5_padconf_global: tisyscon@4a002da0 {
compatible = "syscon";
reg = <0x4A002da0 0xec>;
};
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x40>;
ti,hwmods = "counter_32k";
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
prm: prm@6000 {
compatible = "ti,omap5-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
scrm: scrm@a000 {
compatible = "ti,omap5-scrm";
reg = <0xa000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
omap5_pmx_wkup: pinmux@c840 {
compatible = "ti,omap5-padconf",
"pinctrl-single";
reg = <0xc840 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
};

111
arch/arm/mach-omap2/clock.c
View File

@ -23,6 +23,9 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/of_address.h>
#include <linux/bootmem.h>
#include <asm/cpu.h>
#include <trace/events/power.h>
@ -72,30 +75,110 @@ struct ti_clk_features ti_clk_features;
static bool clkdm_control = true;
static LIST_HEAD(clk_hw_omap_clocks);
void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
struct clk_iomap {
struct regmap *regmap;
void __iomem *mem;
};
static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
static void clk_memmap_writel(u32 val, void __iomem *reg)
{
struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
struct clk_iomap *io = clk_memmaps[r->index];
if (io->regmap)
regmap_write(io->regmap, r->offset, val);
else
writel_relaxed(val, io->mem + r->offset);
}
static u32 clk_memmap_readl(void __iomem *reg)
{
u32 val;
struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
struct clk_iomap *io = clk_memmaps[r->index];
if (io->regmap)
regmap_read(io->regmap, r->offset, &val);
else
val = readl_relaxed(io->mem + r->offset);
return val;
}
void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
{
if (clk->flags & MEMMAP_ADDRESSING) {
struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
writel_relaxed(val, clk_memmaps[r->index] + r->offset);
} else {
if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
writel_relaxed(val, reg);
}
else
clk_memmap_writel(val, reg);
}
u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
{
u32 val;
if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
return readl_relaxed(reg);
else
return clk_memmap_readl(reg);
}
if (clk->flags & MEMMAP_ADDRESSING) {
struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
val = readl_relaxed(clk_memmaps[r->index] + r->offset);
} else {
val = readl_relaxed(reg);
}
static struct ti_clk_ll_ops omap_clk_ll_ops = {
.clk_readl = clk_memmap_readl,
.clk_writel = clk_memmap_writel,
};
return val;
/**
* omap2_clk_provider_init - initialize a clock provider
* @match_table: DT device table to match for devices to init
* @np: device node pointer for the this clock provider
* @index: index for the clock provider
+ @syscon: syscon regmap pointer
* @mem: iomem pointer for the clock provider memory area, only used if
* syscon is not provided
*
* Initializes a clock provider module (CM/PRM etc.), registering
* the memory mapping at specified index and initializing the
* low level driver infrastructure. Returns 0 in success.
*/
int __init omap2_clk_provider_init(struct device_node *np, int index,
struct regmap *syscon, void __iomem *mem)
{
struct clk_iomap *io;
ti_clk_ll_ops = &omap_clk_ll_ops;
io = kzalloc(sizeof(*io), GFP_KERNEL);
io->regmap = syscon;
io->mem = mem;
clk_memmaps[index] = io;
ti_dt_clk_init_provider(np, index);
return 0;
}
/**
* omap2_clk_legacy_provider_init - initialize a legacy clock provider
* @index: index for the clock provider
* @mem: iomem pointer for the clock provider memory area
*
* Initializes a legacy clock provider memory mapping.
*/
void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
{
struct clk_iomap *io;
ti_clk_ll_ops = &omap_clk_ll_ops;
io = memblock_virt_alloc(sizeof(*io), 0);
io->mem = mem;
clk_memmaps[index] = io;
}
/*

8
arch/arm/mach-omap2/clock.h
View File

@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
extern const struct clksel_rate div_1_4_rates[];
extern const struct clksel_rate div31_1to31_rates[];
extern void __iomem *clk_memmaps[];
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
struct regmap;
int __init omap2_clk_provider_init(struct device_node *np, int index,
struct regmap *syscon, void __iomem *mem);
void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
void __init ti_clk_init_features(void);
#endif

2
arch/arm/mach-omap2/cm.h
View File

@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
extern int cm_register(struct cm_ll_data *cld);
extern int cm_unregister(struct cm_ll_data *cld);
int omap_cm_init(void);
int omap2_cm_base_init(void);
# endif

2
arch/arm/mach-omap2/cm2xxx.c
View File

@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
.wait_module_ready = &omap2xxx_cm_wait_module_ready,
};
int __init omap2xxx_cm_init(void)
int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
{
return cm_register(&omap2xxx_cm_ll_data);
}

2
arch/arm/mach-omap2/cm2xxx.h
View File

@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
u32 mdm);
extern int __init omap2xxx_cm_init(void);
int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
#endif

2
arch/arm/mach-omap2/cm33xx.c
View File

@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
.module_disable = &am33xx_cm_module_disable,
};
int __init am33xx_cm_init(void)
int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
{
return cm_register(&am33xx_cm_ll_data);
}

3
arch/arm/mach-omap2/cm33xx.h
View File

@ -19,6 +19,7 @@
#include "cm.h"
#include "cm-regbits-33xx.h"
#include "prcm-common.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000
@ -374,6 +375,6 @@
#ifndef __ASSEMBLER__
int am33xx_cm_init(void);
int am33xx_cm_init(const struct omap_prcm_init_data *data);
#endif /* ASSEMBLER */
#endif

3
arch/arm/mach-omap2/cm3xxx.c
View File

@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
.wait_module_ready = &omap3xxx_cm_wait_module_ready,
};
int __init omap3xxx_cm_init(void)
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
{
omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
return cm_register(&omap3xxx_cm_ll_data);
}

2
arch/arm/mach-omap2/cm3xxx.h
View File

@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
extern void omap3_cm_restore_context(void);
extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
extern int __init omap3xxx_cm_init(void);
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
#endif

3
arch/arm/mach-omap2/cm44xx.h
View File

@ -23,7 +23,6 @@
#define OMAP4_CM_CLKSTCTRL 0x0000
#define OMAP4_CM_STATICDEP 0x0004
void omap_cm_base_init(void);
int omap4_cm_init(void);
int omap4_cm_init(const struct omap_prcm_init_data *data);
#endif

156
arch/arm/mach-omap2/cm_common.c
View File

@ -15,10 +15,14 @@
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/bug.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include "cm2xxx.h"
#include "cm3xxx.h"
#include "cm33xx.h"
#include "cm44xx.h"
#include "clock.h"
/*
* cm_ll_data: function pointers to SoC-specific implementations of
@ -33,6 +37,9 @@ void __iomem *cm_base;
/* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
void __iomem *cm2_base;
#define CM_NO_CLOCKS 0x1
#define CM_SINGLE_INSTANCE 0x2
/**
* omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
* @cm: CM base virtual address
@ -212,3 +219,152 @@ int cm_unregister(struct cm_ll_data *cld)
return 0;
}
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static struct omap_prcm_init_data cm_data __initdata = {
.index = TI_CLKM_CM,
.init = omap4_cm_init,
};
static struct omap_prcm_init_data cm2_data __initdata = {
.index = TI_CLKM_CM2,
.init = omap4_cm_init,
};
#endif
#ifdef CONFIG_ARCH_OMAP2
static struct omap_prcm_init_data omap2_prcm_data __initdata = {
.index = TI_CLKM_CM,
.init = omap2xxx_cm_init,
.flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
};
#endif
#ifdef CONFIG_ARCH_OMAP3
static struct omap_prcm_init_data omap3_cm_data __initdata = {
.index = TI_CLKM_CM,
.init = omap3xxx_cm_init,
.flags = CM_SINGLE_INSTANCE,
/*
* IVA2 offset is a negative value, must offset the cm_base address
* by this to get it to positive side on the iomap
*/
.offset = -OMAP3430_IVA2_MOD,
};
#endif
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
static struct omap_prcm_init_data am3_prcm_data __initdata = {
.index = TI_CLKM_CM,
.flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
.init = am33xx_cm_init,
};
#endif
#ifdef CONFIG_SOC_AM43XX
static struct omap_prcm_init_data am4_prcm_data __initdata = {
.index = TI_CLKM_CM,
.flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE,
.init = omap4_cm_init,
};
#endif
static const struct of_device_id omap_cm_dt_match_table[] __initconst = {
#ifdef CONFIG_ARCH_OMAP2
{ .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data },
#endif
#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-cm", .data = &omap3_cm_data },
#endif
#ifdef CONFIG_ARCH_OMAP4
{ .compatible = "ti,omap4-cm1", .data = &cm_data },
{ .compatible = "ti,omap4-cm2", .data = &cm2_data },
#endif
#ifdef CONFIG_SOC_OMAP5
{ .compatible = "ti,omap5-cm-core-aon", .data = &cm_data },
{ .compatible = "ti,omap5-cm-core", .data = &cm2_data },
#endif
#ifdef CONFIG_SOC_DRA7XX
{ .compatible = "ti,dra7-cm-core-aon", .data = &cm_data },
{ .compatible = "ti,dra7-cm-core", .data = &cm2_data },
#endif
#ifdef CONFIG_SOC_AM33XX
{ .compatible = "ti,am3-prcm", .data = &am3_prcm_data },
#endif
#ifdef CONFIG_SOC_AM43XX
{ .compatible = "ti,am4-prcm", .data = &am4_prcm_data },
#endif
#ifdef CONFIG_SOC_TI81XX
{ .compatible = "ti,dm814-prcm", .data = &am3_prcm_data },
{ .compatible = "ti,dm816-prcm", .data = &am3_prcm_data },
#endif
{ }
};
/**
* omap2_cm_base_init - initialize iomappings for the CM drivers
*
* Detects and initializes the iomappings for the CM driver, based
* on the DT data. Returns 0 in success, negative error value
* otherwise.
*/
int __init omap2_cm_base_init(void)
{
struct device_node *np;
const struct of_device_id *match;
struct omap_prcm_init_data *data;
void __iomem *mem;
for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
data = (struct omap_prcm_init_data *)match->data;
mem = of_iomap(np, 0);
if (!mem)
return -ENOMEM;
if (data->index == TI_CLKM_CM)
cm_base = mem + data->offset;
if (data->index == TI_CLKM_CM2)
cm2_base = mem + data->offset;
data->mem = mem;
data->np = np;
if (data->init && (data->flags & CM_SINGLE_INSTANCE ||
(cm_base && cm2_base)))
data->init(data);
}
return 0;
}
/**
* omap_cm_init - low level init for the CM drivers
*
* Initializes the low level clock infrastructure for CM drivers.
* Returns 0 in success, negative error value in failure.
*/
int __init omap_cm_init(void)
{
struct device_node *np;
const struct of_device_id *match;
const struct omap_prcm_init_data *data;
int ret;
for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) {
data = match->data;
if (data->flags & CM_NO_CLOCKS)
continue;
ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
if (ret)
return ret;
}
return 0;
}

6
arch/arm/mach-omap2/cminst44xx.c
View File

@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
* Populates the base addresses of the _cm_bases
* array used for read/write of cm module registers.
*/
void omap_cm_base_init(void)
static void omap_cm_base_init(void)
{
_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
.module_disable = &omap4_cminst_module_disable,
};
int __init omap4_cm_init(void)
int __init omap4_cm_init(const struct omap_prcm_init_data *data)
{
omap_cm_base_init();
return cm_register(&omap4xxx_cm_ll_data);
}

205
arch/arm/mach-omap2/control.c
View File

@ -14,6 +14,9 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include "soc.h"
#include "iomap.h"
@ -25,13 +28,15 @@
#include "sdrc.h"
#include "pm.h"
#include "control.h"
#include "clock.h"
/* Used by omap3_ctrl_save_padconf() */
#define START_PADCONF_SAVE 0x2
#define PADCONF_SAVE_DONE 0x1
static void __iomem *omap2_ctrl_base;
static void __iomem *omap4_ctrl_pad_base;
static s16 omap2_ctrl_offset;
static struct regmap *omap2_ctrl_syscon;
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
struct omap3_scratchpad {
@ -133,66 +138,79 @@ struct omap3_control_regs {
static struct omap3_control_regs control_context;
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
void __init omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad)
void __init omap2_set_globals_control(void __iomem *ctrl)
{
omap2_ctrl_base = ctrl;
omap4_ctrl_pad_base = ctrl_pad;
}
void __iomem *omap_ctrl_base_get(void)
{
return omap2_ctrl_base;
}
u8 omap_ctrl_readb(u16 offset)
{
return readb_relaxed(OMAP_CTRL_REGADDR(offset));
u32 val;
u8 byte_offset = offset & 0x3;
val = omap_ctrl_readl(offset);
return (val >> (byte_offset * 8)) & 0xff;
}
u16 omap_ctrl_readw(u16 offset)
{
return readw_relaxed(OMAP_CTRL_REGADDR(offset));
u32 val;
u16 byte_offset = offset & 0x2;
val = omap_ctrl_readl(offset);
return (val >> (byte_offset * 8)) & 0xffff;
}
u32 omap_ctrl_readl(u16 offset)
{
return readl_relaxed(OMAP_CTRL_REGADDR(offset));
u32 val;
offset &= 0xfffc;
if (!omap2_ctrl_syscon)
val = readl_relaxed(omap2_ctrl_base + offset);
else
regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
&val);
return val;
}
void omap_ctrl_writeb(u8 val, u16 offset)
{
writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
u32 tmp;
u8 byte_offset = offset & 0x3;
tmp = omap_ctrl_readl(offset);
tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
tmp |= val << (byte_offset * 8);
omap_ctrl_writel(tmp, offset);
}
void omap_ctrl_writew(u16 val, u16 offset)
{
writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
u32 tmp;
u8 byte_offset = offset & 0x2;
tmp = omap_ctrl_readl(offset);
tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
tmp |= val << (byte_offset * 8);
omap_ctrl_writel(tmp, offset);
}
void omap_ctrl_writel(u32 val, u16 offset)
{
writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
}
/*
* On OMAP4 control pad are not addressable from control
* core base. So the common omap_ctrl_read/write APIs breaks
* Hence export separate APIs to manage the omap4 pad control
* registers. This APIs will work only for OMAP4
*/
u32 omap4_ctrl_pad_readl(u16 offset)
{
return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
}
void omap4_ctrl_pad_writel(u32 val, u16 offset)
{
writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
offset &= 0xfffc;
if (!omap2_ctrl_syscon)
writel_relaxed(val, omap2_ctrl_base + offset);
else
regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
val);
}
#ifdef CONFIG_ARCH_OMAP3
@ -611,3 +629,120 @@ void __init omap3_ctrl_init(void)
omap3_ctrl_setup_d2d_padconf();
}
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
struct control_init_data {
int index;
s16 offset;
};
static struct control_init_data ctrl_data = {
.index = TI_CLKM_CTRL,
};
static const struct control_init_data omap2_ctrl_data = {
.index = TI_CLKM_CTRL,
.offset = -OMAP2_CONTROL_GENERAL,
};
static const struct of_device_id omap_scrm_dt_match_table[] = {
{ .compatible = "ti,am3-scm", .data = &ctrl_data },
{ .compatible = "ti,am4-scm", .data = &ctrl_data },
{ .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
{ .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
{ .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
{ }
};
/**
* omap2_control_base_init - initialize iomappings for the control driver
*
* Detects and initializes the iomappings for the control driver, based
* on the DT data. Returns 0 in success, negative error value
* otherwise.
*/
int __init omap2_control_base_init(void)
{
struct device_node *np;
const struct of_device_id *match;
struct control_init_data *data;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
data = (struct control_init_data *)match->data;
omap2_ctrl_base = of_iomap(np, 0);
if (!omap2_ctrl_base)
return -ENOMEM;
omap2_ctrl_offset = data->offset;
}
return 0;
}
/**
* omap_control_init - low level init for the control driver
*
* Initializes the low level clock infrastructure for control driver.
* Returns 0 in success, negative error value in failure.
*/
int __init omap_control_init(void)
{
struct device_node *np, *scm_conf;
const struct of_device_id *match;
const struct omap_prcm_init_data *data;
int ret;
struct regmap *syscon;
for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
data = match->data;
/*
* Check if we have scm_conf node, if yes, use this to
* access clock registers.
*/
scm_conf = of_get_child_by_name(np, "scm_conf");
if (scm_conf) {
syscon = syscon_node_to_regmap(scm_conf);
if (IS_ERR(syscon))
return PTR_ERR(syscon);
omap2_ctrl_syscon = syscon;
if (of_get_child_by_name(scm_conf, "clocks")) {
ret = omap2_clk_provider_init(scm_conf,
data->index,
syscon, NULL);
if (ret)
return ret;
}
iounmap(omap2_ctrl_base);
omap2_ctrl_base = NULL;
} else {
/* No scm_conf found, direct access */
ret = omap2_clk_provider_init(np, data->index, NULL,
omap2_ctrl_base);
if (ret)
return ret;
}
}
return 0;
}
/**
* omap3_control_legacy_iomap_init - legacy iomap init for clock providers
*
* Legacy iomap init for clock provider. Needed only by legacy boot mode,
* where the base addresses are not parsed from DT, but still required
* by the clock driver to be setup properly.
*/
void __init omap3_control_legacy_iomap_init(void)
{
omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
}

10
arch/arm/mach-omap2/control.h
View File

@ -440,15 +440,12 @@
#ifndef __ASSEMBLY__
#ifdef CONFIG_ARCH_OMAP2PLUS
extern void __iomem *omap_ctrl_base_get(void);
extern u8 omap_ctrl_readb(u16 offset);
extern u16 omap_ctrl_readw(u16 offset);
extern u32 omap_ctrl_readl(u16 offset);
extern u32 omap4_ctrl_pad_readl(u16 offset);
extern void omap_ctrl_writeb(u8 val, u16 offset);
extern void omap_ctrl_writew(u16 val, u16 offset);
extern void omap_ctrl_writel(u32 val, u16 offset);
extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
@ -464,10 +461,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
void omap3_ctrl_init(void);
extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
int omap2_control_base_init(void);
int omap_control_init(void);
void omap2_set_globals_control(void __iomem *ctrl);
void __init omap3_control_legacy_iomap_init(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
#define omap_ctrl_readw(x) 0
#define omap_ctrl_readl(x) 0

15
arch/arm/mach-omap2/display.c
View File

@ -26,6 +26,8 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <video/omapdss.h>
#include "omap_hwmod.h"
@ -104,6 +106,10 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
{ "dss_hdmi", "omapdss_hdmi", -1 },
};
#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
static struct regmap *omap4_dsi_mux_syscon;
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
u32 enable_mask, enable_shift;
@ -124,7 +130,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
return -ENODEV;
}
reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
reg &= ~enable_mask;
reg &= ~pipd_mask;
@ -132,7 +138,7 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
reg |= (lanes << enable_shift) & enable_mask;
reg |= (lanes << pipd_shift) & pipd_mask;
omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
return 0;
}
@ -665,5 +671,10 @@ int __init omapdss_init_of(void)
return r;
}
/* add DSI info for omap4 */
node = of_find_node_by_name(NULL, "omap4_padconf_global");
if (node)
omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
return 0;
}

5
arch/arm/mach-omap2/id.c
View File

@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
int omap_type(void)
{
u32 val = 0;
static u32 val = OMAP2_DEVICETYPE_MASK;
if (val < OMAP2_DEVICETYPE_MASK)
return val;
if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);

112
arch/arm/mach-omap2/io.c
View File

@ -382,13 +382,9 @@ void __init omap2420_init_early(void)
omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
omap2_control_base_init();
omap2xxx_check_revision();
omap2xxx_prm_init();
omap2xxx_cm_init();
omap2_prcm_base_init();
omap2xxx_voltagedomains_init();
omap242x_powerdomains_init();
omap242x_clockdomains_init();
@ -412,13 +408,9 @@ void __init omap2430_init_early(void)
omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
omap2_control_base_init();
omap2xxx_check_revision();
omap2xxx_prm_init();
omap2xxx_cm_init();
omap2_prcm_base_init();
omap2xxx_voltagedomains_init();
omap243x_powerdomains_init();
omap243x_clockdomains_init();
@ -446,21 +438,30 @@ void __init omap3_init_early(void)
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
/* XXX: remove these once OMAP3 is DT only */
if (!of_have_populated_dt()) {
omap2_set_globals_control(
OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
NULL);
}
omap2_control_base_init();
omap3xxx_check_revision();
omap3xxx_check_features();
omap3xxx_prm_init();
omap3xxx_cm_init();
omap2_prcm_base_init();
/* XXX: remove these once OMAP3 is DT only */
if (!of_have_populated_dt()) {
omap3xxx_prm_init(NULL);
omap3xxx_cm_init(NULL);
}
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
omap3xxx_hwmod_init();
omap_hwmod_init_postsetup();
if (!of_have_populated_dt()) {
omap3_prcm_legacy_iomaps_init();
omap3_control_legacy_iomap_init();
if (soc_is_am35xx())
omap_clk_soc_init = am35xx_clk_legacy_init;
else if (cpu_is_omap3630())
@ -547,14 +548,10 @@ void __init ti814x_init_early(void)
{
omap2_set_globals_tap(TI814X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap2_control_base_init();
omap3xxx_check_revision();
ti81xx_check_features();
am33xx_prm_init();
am33xx_cm_init();
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti81xx_clockdomains_init();
@ -568,14 +565,10 @@ void __init ti816x_init_early(void)
{
omap2_set_globals_tap(TI816X_CLASS,
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap2_control_base_init();
omap3xxx_check_revision();
ti81xx_check_features();
am33xx_prm_init();
am33xx_cm_init();
omap2_prcm_base_init();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
ti81xx_clockdomains_init();
@ -591,14 +584,10 @@ void __init am33xx_init_early(void)
{
omap2_set_globals_tap(AM335X_CLASS,
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
am33xx_prm_init();
am33xx_cm_init();
omap2_prcm_base_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
am33xx_hwmod_init();
@ -617,16 +606,10 @@ void __init am43xx_init_early(void)
{
omap2_set_globals_tap(AM335X_CLASS,
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
NULL);
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
omap_prm_base_init();
omap_cm_base_init();
omap2_control_base_init();
omap3xxx_check_revision();
am33xx_check_features();
omap44xx_prm_init();
omap4_cm_init();
omap2_prcm_base_init();
am43xx_powerdomains_init();
am43xx_clockdomains_init();
am43xx_hwmod_init();
@ -646,19 +629,12 @@ void __init omap4430_init_early(void)
{
omap2_set_globals_tap(OMAP443X_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
omap_prm_base_init();
omap_cm_base_init();
omap2_control_base_init();
omap4xxx_check_revision();
omap4xxx_check_features();
omap4_cm_init();
omap2_prcm_base_init();
omap4_pm_init_early();
omap44xx_prm_init();
omap44xx_voltagedomains_init();
omap44xx_powerdomains_init();
omap44xx_clockdomains_init();
@ -681,18 +657,11 @@ void __init omap5_init_early(void)
{
omap2_set_globals_tap(OMAP54XX_CLASS,
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap2_control_base_init();
omap4_pm_init_early();
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
omap2_prcm_base_init();
omap5xxx_check_revision();
omap4_cm_init();
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();
@ -713,18 +682,11 @@ void __init omap5_init_late(void)
void __init dra7xx_init_early(void)
{
omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap2_control_base_init();
omap4_pm_init_early();
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
omap2_prcm_base_init();
dra7xxx_check_revision();
omap4_cm_init();
dra7xx_powerdomains_init();
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
@ -762,7 +724,11 @@ int __init omap_clk_init(void)
ti_clk_init_features();
if (of_have_populated_dt()) {
ret = of_prcm_init();
ret = omap_control_init();
if (ret)
return ret;
ret = omap_prcm_init();
if (ret)
return ret;

24
arch/arm/mach-omap2/pm24xx.c
View File

@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void)
/* Clear old wake-up events */
/* REVISIT: These write to reserved bits? */
omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
@ -104,18 +104,16 @@ no_sleep:
clk_enable(osc_ck);
/* clear CORE wake-up events */
omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
/* MPU domain wake events */
omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
0x1);
omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET,
0x20);
omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
@ -143,9 +141,9 @@ static void omap2_enter_mpu_retention(void)
* it is in retention mode. */
if (omap2_allow_mpu_retention()) {
/* REVISIT: These write to reserved bits? */
omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
/* Try to enter MPU retention */
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

18
arch/arm/mach-omap2/pm34xx.c
View File

@ -137,9 +137,8 @@ static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
{
int c;
c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
~(OMAP3430_ST_IO_MASK |
OMAP3430_ST_IO_CHAIN_MASK));
c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, OMAP3430_ST_IO_MASK |
OMAP3430_ST_IO_CHAIN_MASK);
return c ? IRQ_HANDLED : IRQ_NONE;
}
@ -153,14 +152,13 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
* these are handled in a separate handler to avoid acking
* IO events before parsing in mux code
*/
c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1,
OMAP3430_ST_IO_MASK |
OMAP3430_ST_IO_CHAIN_MASK);
c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0);
c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
c = omap_prm_clear_mod_irqs(WKUP_MOD, 1, ~(OMAP3430_ST_IO_MASK |
OMAP3430_ST_IO_CHAIN_MASK));
c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0);
c += omap_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, ~0);
if (omap_rev() > OMAP3430_REV_ES1_0) {
c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0);
c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0);
c += omap_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, ~0);
}
return c ? IRQ_HANDLED : IRQ_NONE;

20
arch/arm/mach-omap2/prcm-common.h
View File

@ -518,6 +518,26 @@ struct omap_prcm_irq_setup {
.priority = _priority \
}
/**
* struct omap_prcm_init_data - PRCM driver init data
* @index: clock memory mapping index to be used
* @mem: IO mem pointer for this module
* @offset: module base address offset from the IO base
* @flags: PRCM module init flags
* @device_inst_offset: device instance offset within the module address space
* @init: low level PRCM init function for this module
* @np: device node for this PRCM module
*/
struct omap_prcm_init_data {
int index;
void __iomem *mem;
s16 offset;
u16 flags;
s32 device_inst_offset;
int (*init)(const struct omap_prcm_init_data *data);
struct device_node *np;
};
extern void omap_prcm_irq_cleanup(void);
extern int omap_prcm_register_chain_handler(
struct omap_prcm_irq_setup *irq_setup);

27
arch/arm/mach-omap2/prm.h
View File

@ -19,8 +19,9 @@
extern void __iomem *prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int of_prcm_init(void);
void omap3_prcm_legacy_iomaps_init(void);
int omap_prcm_init(void);
int omap2_prm_base_init(void);
int omap2_prcm_base_init(void);
# endif
/*
@ -28,9 +29,11 @@ void omap3_prcm_legacy_iomaps_init(void);
*
* PRM_HAS_IO_WAKEUP: has IO wakeup capability
* PRM_HAS_VOLTAGE: has voltage domains
* PRM_IRQ_DEFAULT: use default irq number for PRM irq
*/
#define PRM_HAS_IO_WAKEUP (1 << 0)
#define PRM_HAS_VOLTAGE (1 << 1)
#define PRM_HAS_IO_WAKEUP BIT(0)
#define PRM_HAS_VOLTAGE BIT(1)
#define PRM_IRQ_DEFAULT BIT(2)
/*
* MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@ -146,6 +149,9 @@ struct prm_ll_data {
int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
u16 offset);
void (*reset_system)(void);
int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
u32 (*vp_check_txdone)(u8 vp_id);
void (*vp_clear_txdone)(u8 vp_id);
};
extern int prm_register(struct prm_ll_data *pld);
@ -161,6 +167,19 @@ extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
void omap_prm_reset_system(void);
void omap_prm_reconfigure_io_chain(void);
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
/*
* Voltage Processor (VP) identifiers
*/
#define OMAP3_VP_VDD_MPU_ID 0
#define OMAP3_VP_VDD_CORE_ID 1
#define OMAP4_VP_VDD_CORE_ID 0
#define OMAP4_VP_VDD_IVA_ID 1
#define OMAP4_VP_VDD_MPU_ID 2
u32 omap_prm_vp_check_txdone(u8 vp_id);
void omap_prm_vp_clear_txdone(u8 vp_id);
#endif

6
arch/arm/mach-omap2/prm2xxx.c
View File

@ -123,13 +123,14 @@ static void omap2xxx_prm_dpll_reset(void)
* Clears wakeup status bits for a given module, so that the device can
* re-enter idle.
*/
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
{
u32 wkst;
wkst = omap2_prm_read_mod_reg(module, regs);
wkst &= wkst_mask;
omap2_prm_write_mod_reg(wkst, module, regs);
return 0;
}
int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
@ -216,9 +217,10 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
.deassert_hardreset = &omap2_prm_deassert_hardreset,
.is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
.reset_system = &omap2xxx_prm_dpll_reset,
.clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
};
int __init omap2xxx_prm_init(void)
int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
{
return prm_register(&omap2xxx_prm_ll_data);
}

4
arch/arm/mach-omap2/prm2xxx.h
View File

@ -124,9 +124,7 @@
extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);
extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
extern int __init omap2xxx_prm_init(void);
int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data);
#endif

2
arch/arm/mach-omap2/prm33xx.c
View File

@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
.reset_system = am33xx_prm_global_warm_sw_reset,
};
int __init am33xx_prm_init(void)
int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
{
return prm_register(&am33xx_prm_ll_data);
}

2
arch/arm/mach-omap2/prm33xx.h
View File

@ -118,7 +118,7 @@
#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
#ifndef __ASSEMBLER__
int am33xx_prm_init(void);
int am33xx_prm_init(const struct omap_prcm_init_data *data);
#endif /* ASSEMBLER */
#endif

20
arch/arm/mach-omap2/prm3xxx.c
View File

@ -29,6 +29,7 @@
#include "prm-regbits-34xx.h"
#include "cm3xxx.h"
#include "cm-regbits-34xx.h"
#include "clock.h"
static void omap3xxx_prm_read_pending_irqs(unsigned long *events);
static void omap3xxx_prm_ocp_barrier(void);
@ -96,7 +97,7 @@ static struct omap3_vp omap3_vp[] = {
#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
u32 omap3_prm_vp_check_txdone(u8 vp_id)
static u32 omap3_prm_vp_check_txdone(u8 vp_id)
{
struct omap3_vp *vp = &omap3_vp[vp_id];
u32 irqstatus;
@ -106,7 +107,7 @@ u32 omap3_prm_vp_check_txdone(u8 vp_id)
return irqstatus & vp->tranxdone_status;
}
void omap3_prm_vp_clear_txdone(u8 vp_id)
static void omap3_prm_vp_clear_txdone(u8 vp_id)
{
struct omap3_vp *vp = &omap3_vp[vp_id];
@ -217,7 +218,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
* omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
* @module: PRM module to clear wakeups from
* @regs: register set to clear, 1 or 3
* @ignore_bits: wakeup status bits to ignore
* @wkst_mask: wkst bits to clear
*
* The purpose of this function is to clear any wake-up events latched
* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
@ -226,7 +227,7 @@ static void omap3xxx_prm_restore_irqen(u32 *saved_mask)
* that any peripheral wake-up events occurring while attempting to
* clear the PM_WKST_x are detected and cleared.
*/
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
{
u32 wkst, fclk, iclk, clken;
u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@ -238,7 +239,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
wkst &= ~ignore_bits;
wkst &= wkst_mask;
if (wkst) {
iclk = omap2_cm_read_mod_reg(module, iclk_off);
fclk = omap2_cm_read_mod_reg(module, fclk_off);
@ -254,7 +255,7 @@ int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
omap2_prm_write_mod_reg(wkst, module, wkst_off);
wkst = omap2_prm_read_mod_reg(module, wkst_off);
wkst &= ~ignore_bits;
wkst &= wkst_mask;
c++;
}
omap2_cm_write_mod_reg(iclk, module, iclk_off);
@ -664,10 +665,15 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
.deassert_hardreset = &omap2_prm_deassert_hardreset,
.is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
.reset_system = &omap3xxx_prm_dpll3_reset,
.clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs,
.vp_check_txdone = &omap3_prm_vp_check_txdone,
.vp_clear_txdone = &omap3_prm_vp_clear_txdone,
};
int __init omap3xxx_prm_init(void)
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data)
{
omap2_clk_legacy_provider_init(TI_CLKM_PRM,
prm_base + OMAP3430_IVA2_MOD);
if (omap3_has_io_wakeup())
prm_features |= PRM_HAS_IO_WAKEUP;

7
arch/arm/mach-omap2/prm3xxx.h
View File

@ -132,10 +132,6 @@
#ifndef __ASSEMBLER__
/* OMAP3-specific VP functions */
u32 omap3_prm_vp_check_txdone(u8 vp_id);
void omap3_prm_vp_clear_txdone(u8 vp_id);
/*
* OMAP3 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
@ -144,8 +140,7 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
extern void omap3_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern int __init omap3xxx_prm_init(void);
int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits);
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data);
void omap3xxx_prm_iva_idle(void);
void omap3_prm_reset_modem(void);
int omap3xxx_prm_clear_global_cold_reset(void);

66
arch/arm/mach-omap2/prm44xx.c
View File

@ -138,7 +138,7 @@ static struct omap4_vp omap4_vp[] = {
},
};
u32 omap4_prm_vp_check_txdone(u8 vp_id)
static u32 omap4_prm_vp_check_txdone(u8 vp_id)
{
struct omap4_vp *vp = &omap4_vp[vp_id];
u32 irqstatus;
@ -149,7 +149,7 @@ u32 omap4_prm_vp_check_txdone(u8 vp_id)
return irqstatus & vp->tranxdone_status;
}
void omap4_prm_vp_clear_txdone(u8 vp_id)
static void omap4_prm_vp_clear_txdone(u8 vp_id)
{
struct omap4_vp *vp = &omap4_vp[vp_id];
@ -699,29 +699,31 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
.deassert_hardreset = omap4_prminst_deassert_hardreset,
.is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
.reset_system = omap4_prminst_global_warm_sw_reset,
.vp_check_txdone = omap4_prm_vp_check_txdone,
.vp_clear_txdone = omap4_prm_vp_clear_txdone,
};
int __init omap44xx_prm_init(void)
static const struct omap_prcm_init_data *prm_init_data;
int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
{
if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
omap_prm_base_init();
prm_init_data = data;
if (data->flags & PRM_HAS_IO_WAKEUP)
prm_features |= PRM_HAS_IO_WAKEUP;
if (!soc_is_dra7xx())
if (data->flags & PRM_HAS_VOLTAGE)
prm_features |= PRM_HAS_VOLTAGE;
omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
return prm_register(&omap44xx_prm_ll_data);
}
static const struct of_device_id omap_prm_dt_match_table[] = {
{ .compatible = "ti,omap4-prm" },
{ .compatible = "ti,omap5-prm" },
{ .compatible = "ti,dra7-prm" },
{ }
};
static int omap44xx_prm_late_init(void)
{
struct device_node *np;
int irq_num;
if (!(prm_features & PRM_HAS_IO_WAKEUP))
@ -731,31 +733,23 @@ static int omap44xx_prm_late_init(void)
if (!of_have_populated_dt())
return 0;
np = of_find_matching_node(NULL, omap_prm_dt_match_table);
irq_num = of_irq_get(prm_init_data->np, 0);
/*
* Already have OMAP4 IRQ num. For all other platforms, we need
* IRQ numbers from DT
*/
if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
if (irq_num == -EPROBE_DEFER)
return irq_num;
if (!np) {
/* Default loaded up with OMAP4 values */
if (!cpu_is_omap44xx())
return 0;
} else {
irq_num = of_irq_get(np, 0);
/*
* Already have OMAP4 IRQ num. For all other platforms, we need
* IRQ numbers from DT
*/
if (irq_num < 0 && !cpu_is_omap44xx()) {
if (irq_num == -EPROBE_DEFER)
return irq_num;
/* Have nothing to do */
return 0;
}
/* Have nothing to do */
return 0;
}
/* Once OMAP4 DT is filled as well */
if (irq_num >= 0) {
omap4_prcm_irq_setup.irq = irq_num;
omap4_prcm_irq_setup.xlate_irq = NULL;
}
/* Once OMAP4 DT is filled as well */
if (irq_num >= 0) {
omap4_prcm_irq_setup.irq = irq_num;
omap4_prcm_irq_setup.xlate_irq = NULL;
}
omap44xx_prm_enable_io_wakeup();

1
arch/arm/mach-omap2/prm44xx.h
View File

@ -26,7 +26,6 @@
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm.h"
#define OMAP4430_PRM_BASE 0x4a306000

8
arch/arm/mach-omap2/prm44xx_54xx.h
View File

@ -23,13 +23,11 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
#include "prcm-common.h"
/* Function prototypes */
#ifndef __ASSEMBLER__
/* OMAP4/OMAP5-specific VP functions */
u32 omap4_prm_vp_check_txdone(u8 vp_id);
void omap4_prm_vp_clear_txdone(u8 vp_id);
/*
* OMAP4/OMAP5 access functions for voltage controller (VC) and
* voltage proccessor (VP) in the PRM.
@ -38,7 +36,7 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
extern int __init omap44xx_prm_init(void);
int __init omap44xx_prm_init(const struct omap_prcm_init_data *data);
#endif

1
arch/arm/mach-omap2/prm54xx.h
View File

@ -22,7 +22,6 @@
#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm.h"
#define OMAP54XX_PRM_BASE 0x4ae06000

2
arch/arm/mach-omap2/prm7xx.h
View File

@ -22,8 +22,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm44xx_54xx.h"
#include "prm.h"
#define DRA7XX_PRM_BASE 0x4ae06000

268
arch/arm/mach-omap2/prm_common.c
View File

@ -32,7 +32,11 @@
#include "prm2xxx_3xxx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm33xx.h"
#include "prm44xx.h"
#include "prm54xx.h"
#include "prm7xx.h"
#include "prcm43xx.h"
#include "common.h"
#include "clock.h"
#include "cm.h"
@ -533,6 +537,61 @@ void omap_prm_reset_system(void)
cpu_relax();
}
/**
* omap_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt
* @module: PRM module to clear wakeups from
* @regs: register to clear
* @wkst_mask: wkst bits to clear
*
* Clears any wakeup events for the module and register set defined.
* Uses SoC specific implementation to do the actual wakeup status
* clearing.
*/
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
{
if (!prm_ll_data->clear_mod_irqs) {
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
__func__);
return -EINVAL;
}
return prm_ll_data->clear_mod_irqs(module, regs, wkst_mask);
}
/**
* omap_prm_vp_check_txdone - check voltage processor TX done status
*
* Checks if voltage processor transmission has been completed.
* Returns non-zero if a transmission has completed, 0 otherwise.
*/
u32 omap_prm_vp_check_txdone(u8 vp_id)
{
if (!prm_ll_data->vp_check_txdone) {
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
__func__);
return 0;
}
return prm_ll_data->vp_check_txdone(vp_id);
}
/**
* omap_prm_vp_clear_txdone - clears voltage processor TX done status
*
* Clears the status bit for completed voltage processor transmission
* returned by prm_vp_check_txdone.
*/
void omap_prm_vp_clear_txdone(u8 vp_id)
{
if (!prm_ll_data->vp_clear_txdone) {
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
__func__);
return;
}
prm_ll_data->vp_clear_txdone(vp_id);
}
/**
* prm_register - register per-SoC low-level data with the PRM
* @pld: low-level per-SoC OMAP PRM data & function pointers to register
@ -578,78 +637,175 @@ int prm_unregister(struct prm_ll_data *pld)
return 0;
}
static const struct of_device_id omap_prcm_dt_match_table[] = {
{ .compatible = "ti,am3-prcm" },
{ .compatible = "ti,am3-scrm" },
{ .compatible = "ti,am4-prcm" },
{ .compatible = "ti,am4-scrm" },
{ .compatible = "ti,dm814-prcm" },
{ .compatible = "ti,dm814-scrm" },
{ .compatible = "ti,dm816-prcm" },
{ .compatible = "ti,dm816-scrm" },
{ .compatible = "ti,omap2-prcm" },
{ .compatible = "ti,omap2-scrm" },
{ .compatible = "ti,omap3-prm" },
{ .compatible = "ti,omap3-cm" },
{ .compatible = "ti,omap3-scrm" },
{ .compatible = "ti,omap4-cm1" },
{ .compatible = "ti,omap4-prm" },
{ .compatible = "ti,omap4-cm2" },
{ .compatible = "ti,omap4-scrm" },
{ .compatible = "ti,omap5-prm" },
{ .compatible = "ti,omap5-cm-core-aon" },
{ .compatible = "ti,omap5-scrm" },
{ .compatible = "ti,omap5-cm-core" },
{ .compatible = "ti,dra7-prm" },
{ .compatible = "ti,dra7-cm-core-aon" },
{ .compatible = "ti,dra7-cm-core" },
#ifdef CONFIG_ARCH_OMAP2
static struct omap_prcm_init_data omap2_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap2xxx_prm_init,
};
#endif
#ifdef CONFIG_ARCH_OMAP3
static struct omap_prcm_init_data omap3_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap3xxx_prm_init,
/*
* IVA2 offset is a negative value, must offset the prm_base
* address by this to get it to positive
*/
.offset = -OMAP3430_IVA2_MOD,
};
#endif
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX)
static struct omap_prcm_init_data am3_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = am33xx_prm_init,
};
#endif
#ifdef CONFIG_ARCH_OMAP4
static struct omap_prcm_init_data omap4_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = OMAP4430_PRM_DEVICE_INST,
.flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE | PRM_IRQ_DEFAULT,
};
#endif
#ifdef CONFIG_SOC_OMAP5
static struct omap_prcm_init_data omap5_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = OMAP54XX_PRM_DEVICE_INST,
.flags = PRM_HAS_IO_WAKEUP | PRM_HAS_VOLTAGE,
};
#endif
#ifdef CONFIG_SOC_DRA7XX
static struct omap_prcm_init_data dra7_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = DRA7XX_PRM_DEVICE_INST,
.flags = PRM_HAS_IO_WAKEUP,
};
#endif
#ifdef CONFIG_SOC_AM43XX
static struct omap_prcm_init_data am4_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = omap44xx_prm_init,
.device_inst_offset = AM43XX_PRM_DEVICE_INST,
};
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
static struct omap_prcm_init_data scrm_data __initdata = {
.index = TI_CLKM_SCRM,
};
#endif
static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
#ifdef CONFIG_SOC_AM33XX
{ .compatible = "ti,am3-prcm", .data = &am3_prm_data },
#endif
#ifdef CONFIG_SOC_AM43XX
{ .compatible = "ti,am4-prcm", .data = &am4_prm_data },
#endif
#ifdef CONFIG_SOC_TI81XX
{ .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
#endif
#ifdef CONFIG_ARCH_OMAP2
{ .compatible = "ti,omap2-prcm", .data = &omap2_prm_data },
#endif
#ifdef CONFIG_ARCH_OMAP3
{ .compatible = "ti,omap3-prm", .data = &omap3_prm_data },
#endif
#ifdef CONFIG_ARCH_OMAP4
{ .compatible = "ti,omap4-prm", .data = &omap4_prm_data },
{ .compatible = "ti,omap4-scrm", .data = &scrm_data },
#endif
#ifdef CONFIG_SOC_OMAP5
{ .compatible = "ti,omap5-prm", .data = &omap5_prm_data },
{ .compatible = "ti,omap5-scrm", .data = &scrm_data },
#endif
#ifdef CONFIG_SOC_DRA7XX
{ .compatible = "ti,dra7-prm", .data = &dra7_prm_data },
#endif
{ }
};
static struct clk_hw_omap memmap_dummy_ck = {
.flags = MEMMAP_ADDRESSING,
};
static u32 prm_clk_readl(void __iomem *reg)
{
return omap2_clk_readl(&memmap_dummy_ck, reg);
}
static void prm_clk_writel(u32 val, void __iomem *reg)
{
omap2_clk_writel(val, &memmap_dummy_ck, reg);
}
static struct ti_clk_ll_ops omap_clk_ll_ops = {
.clk_readl = prm_clk_readl,
.clk_writel = prm_clk_writel,
};
int __init of_prcm_init(void)
/**
* omap2_prm_base_init - initialize iomappings for the PRM driver
*
* Detects and initializes the iomappings for the PRM driver, based
* on the DT data. Returns 0 in success, negative error value
* otherwise.
*/
int __init omap2_prm_base_init(void)
{
struct device_node *np;
const struct of_device_id *match;
struct omap_prcm_init_data *data;
void __iomem *mem;
int memmap_index = 0;
ti_clk_ll_ops = &omap_clk_ll_ops;
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
data = (struct omap_prcm_init_data *)match->data;
for_each_matching_node(np, omap_prcm_dt_match_table) {
mem = of_iomap(np, 0);
clk_memmaps[memmap_index] = mem;
ti_dt_clk_init_provider(np, memmap_index);
memmap_index++;
if (!mem)
return -ENOMEM;
if (data->index == TI_CLKM_PRM)
prm_base = mem + data->offset;
data->mem = mem;
data->np = np;
if (data->init)
data->init(data);
}
return 0;
}
void __init omap3_prcm_legacy_iomaps_init(void)
int __init omap2_prcm_base_init(void)
{
ti_clk_ll_ops = &omap_clk_ll_ops;
int ret;
clk_memmaps[TI_CLKM_CM] = cm_base + OMAP3430_IVA2_MOD;
clk_memmaps[TI_CLKM_PRM] = prm_base + OMAP3430_IVA2_MOD;
clk_memmaps[TI_CLKM_SCRM] = omap_ctrl_base_get();
ret = omap2_prm_base_init();
if (ret)
return ret;
return omap2_cm_base_init();
}
/**
* omap_prcm_init - low level init for the PRCM drivers
*
* Initializes the low level clock infrastructure for PRCM drivers.
* Returns 0 in success, negative error value in failure.
*/
int __init omap_prcm_init(void)
{
struct device_node *np;
const struct of_device_id *match;
const struct omap_prcm_init_data *data;
int ret;
for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) {
data = match->data;
ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
if (ret)
return ret;
}
omap_cm_init();
return 0;
}
static int __init prm_late_init(void)

18
arch/arm/mach-omap2/prminst44xx.c
View File

@ -47,22 +47,14 @@ void omap_prm_base_init(void)
s32 omap4_prmst_get_prm_dev_inst(void)
{
if (prm_dev_inst != PRM_INSTANCE_UNKNOWN)
return prm_dev_inst;
/* This cannot be done way early at boot.. as things are not setup */
if (cpu_is_omap44xx())
prm_dev_inst = OMAP4430_PRM_DEVICE_INST;
else if (soc_is_omap54xx())
prm_dev_inst = OMAP54XX_PRM_DEVICE_INST;
else if (soc_is_dra7xx())
prm_dev_inst = DRA7XX_PRM_DEVICE_INST;
else if (soc_is_am43xx())
prm_dev_inst = AM43XX_PRM_DEVICE_INST;
return prm_dev_inst;
}
void omap4_prminst_set_prm_dev_inst(s32 dev_inst)
{
prm_dev_inst = dev_inst;
}
/* Read a register in a PRM instance */
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{

1
arch/arm/mach-omap2/prminst44xx.h
View File

@ -14,6 +14,7 @@
#define PRM_INSTANCE_UNKNOWN -1
extern s32 omap4_prmst_get_prm_dev_inst(void);
void omap4_prminst_set_prm_dev_inst(s32 dev_inst);
/*
* In an ideal world, we would not export these low-level functions,

9
arch/arm/mach-omap2/vp.h
View File

@ -21,15 +21,6 @@
struct voltagedomain;
/*
* Voltage Processor (VP) identifiers
*/
#define OMAP3_VP_VDD_MPU_ID 0
#define OMAP3_VP_VDD_CORE_ID 1
#define OMAP4_VP_VDD_CORE_ID 0
#define OMAP4_VP_VDD_IVA_ID 1
#define OMAP4_VP_VDD_MPU_ID 2
/* XXX document */
#define VP_IDLE_TIMEOUT 200
#define VP_TRANXDONE_TIMEOUT 300

4
arch/arm/mach-omap2/vp3xxx_data.c
View File

@ -28,8 +28,8 @@
#include "prm2xxx_3xxx.h"
static const struct omap_vp_ops omap3_vp_ops = {
.check_txdone = omap3_prm_vp_check_txdone,
.clear_txdone = omap3_prm_vp_clear_txdone,
.check_txdone = omap_prm_vp_check_txdone,
.clear_txdone = omap_prm_vp_clear_txdone,
};
/*

4
arch/arm/mach-omap2/vp44xx_data.c
View File

@ -28,8 +28,8 @@
#include "vp.h"
static const struct omap_vp_ops omap4_vp_ops = {
.check_txdone = omap4_prm_vp_check_txdone,
.clear_txdone = omap4_prm_vp_clear_txdone,
.check_txdone = omap_prm_vp_check_txdone,
.clear_txdone = omap_prm_vp_clear_txdone,
};
/*

5
drivers/clk/ti/apll.c
View File

@ -203,7 +203,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
ad->control_reg = ti_clk_get_reg_addr(node, 0);
ad->idlest_reg = ti_clk_get_reg_addr(node, 1);
if (!ad->control_reg || !ad->idlest_reg)
if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg))
goto cleanup;
ad->idlest_mask = 0x1;
@ -384,7 +384,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
ad->autoidle_reg = ti_clk_get_reg_addr(node, 1);
ad->idlest_reg = ti_clk_get_reg_addr(node, 2);
if (!ad->control_reg || !ad->autoidle_reg || !ad->idlest_reg)
if (IS_ERR(ad->control_reg) || IS_ERR(ad->autoidle_reg) ||
IS_ERR(ad->idlest_reg))
goto cleanup;
clk = clk_register(NULL, &clk_hw->hw);

2
drivers/clk/ti/autoidle.c
View File

@ -119,7 +119,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
clk->name = node->name;
clk->reg = ti_clk_get_reg_addr(node, 0);
if (!clk->reg) {
if (IS_ERR(clk->reg)) {
kfree(clk);
return -EINVAL;
}

7
drivers/clk/ti/clk.c
View File

@ -103,7 +103,8 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
* @index: register index from the clock node
*
* Builds clock register address from device tree information. This
* is a struct of type clk_omap_reg.
* is a struct of type clk_omap_reg. Returns a pointer to the register
* address, or a pointer error value in failure.
*/
void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
{
@ -121,14 +122,14 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
if (i == CLK_MAX_MEMMAPS) {
pr_err("clk-provider not found for %s!\n", node->name);
return NULL;
return ERR_PTR(-ENOENT);
}
reg->index = i;
if (of_property_read_u32_index(node, "reg", index, &val)) {
pr_err("%s must have reg[%d]!\n", node->name, index);
return NULL;
return ERR_PTR(-EINVAL);
}
reg->offset = val;

4
drivers/clk/ti/divider.c
View File

@ -530,8 +530,8 @@ static int __init ti_clk_divider_populate(struct device_node *node,
u32 val;
*reg = ti_clk_get_reg_addr(node, 0);
if (!*reg)
return -EINVAL;
if (IS_ERR(*reg))
return PTR_ERR(*reg);
if (!of_property_read_u32(node, "ti,bit-shift", &val))
*shift = val;

6
drivers/clk/ti/dpll.c
View File

@ -390,18 +390,18 @@ static void __init of_ti_dpll_setup(struct device_node *node,
#endif
} else {
dd->idlest_reg = ti_clk_get_reg_addr(node, 1);
if (!dd->idlest_reg)
if (IS_ERR(dd->idlest_reg))
goto cleanup;
dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2);
}
if (!dd->control_reg || !dd->mult_div1_reg)
if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
goto cleanup;
if (dd->autoidle_mask) {
dd->autoidle_reg = ti_clk_get_reg_addr(node, 3);
if (!dd->autoidle_reg)
if (IS_ERR(dd->autoidle_reg))
goto cleanup;
}

4
drivers/clk/ti/gate.c
View File

@ -225,7 +225,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
if (ops != &omap_gate_clkdm_clk_ops) {
reg = ti_clk_get_reg_addr(node, 0);
if (!reg)
if (IS_ERR(reg))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))
@ -264,7 +264,7 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
return;
gate->enable_reg = ti_clk_get_reg_addr(node, 0);
if (!gate->enable_reg)
if (IS_ERR(gate->enable_reg))
goto cleanup;
of_property_read_u32(node, "ti,bit-shift", &val);

2
drivers/clk/ti/interface.c
View File

@ -111,7 +111,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
u32 val;
reg = ti_clk_get_reg_addr(node, 0);
if (!reg)
if (IS_ERR(reg))
return;
if (!of_property_read_u32(node, "ti,bit-shift", &val))

4
drivers/clk/ti/mux.c
View File

@ -210,7 +210,7 @@ static void of_mux_clk_setup(struct device_node *node)
reg = ti_clk_get_reg_addr(node, 0);
if (!reg)
if (IS_ERR(reg))
goto cleanup;
of_property_read_u32(node, "ti,bit-shift", &shift);
@ -283,7 +283,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
mux->reg = ti_clk_get_reg_addr(node, 0);
if (!mux->reg)
if (IS_ERR(mux->reg))
goto cleanup;
if (!of_property_read_u32(node, "ti,bit-shift", &val))

6
include/linux/clk/ti.h
View File

@ -215,14 +215,14 @@ struct ti_dt_clk {
.node_name = name, \
}
/* Maximum number of clock memmaps */
#define CLK_MAX_MEMMAPS 4
/* Static memmap indices */
enum {
TI_CLKM_CM = 0,
TI_CLKM_CM2,
TI_CLKM_PRM,
TI_CLKM_SCRM,
TI_CLKM_CTRL,
CLK_MAX_MEMMAPS
};
typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);