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[SCSI] mvsas: add support for 94xx; layout change; bug fixes

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This version contains following main changes
  - Switch to new layout to support more types of ASIC.
  - SSP TMF supported and related Error Handing enhanced.
  - Support flash feature with delay 2*HZ when PHY changed.
  - Support Marvell 94xx series ASIC for 6G SAS/SATA, which has 2
88SE64xx chips but any different register description.
  - Support SPI flash for HBA-related configuration info.
  - Other patch enhanced from kernel side such as increasing PHY type

[jejb: fold back in DMA_BIT_MASK changes]
Signed-off-by: Ying Chu <jasonchu@marvell.com>
Signed-off-by: Andy Yan <ayan@marvell.com>
Signed-off-by: Ke Wei <kewei@marvell.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com>
This commit is contained in:
Andy Yan 2009-05-08 17:46:40 -04:00 committed by James Bottomley
parent dd4969a892
commit 20b09c2992
11 changed files with 3915 additions and 1399 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/scsi/mvsas/Kconfig
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@ -1,35 +1,42 @@
# #
# Kernel configuration file for 88SE64XX SAS/SATA driver. # Kernel configuration file for 88SE64XX/88SE94XX SAS/SATA driver.
# #
# Copyright 2007 Red Hat, Inc. # Copyright 2007 Red Hat, Inc.
# Copyright 2008 Marvell. <kewei@marvell.com> # Copyright 2008 Marvell. <kewei@marvell.com>
# #
# This file is licensed under GPLv2. # This file is licensed under GPLv2.
# #
# This file is part of the 88SE64XX driver. # This file is part of the 88SE64XX/88SE94XX driver.
# #
# The 88SE64XX driver is free software; you can redistribute # The 88SE64XX/88SE94XX driver is free software; you can redistribute
# it and/or modify it under the terms of the GNU General Public License # it and/or modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; version 2 of the # as published by the Free Software Foundation; version 2 of the
# License. # License.
# #
# The 88SE64XX driver is distributed in the hope that it will be # The 88SE64XX/88SE94XX driver is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of # useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details. # General Public License for more details.
# #
# You should have received a copy of the GNU General Public License # You should have received a copy of the GNU General Public License
# along with 88SE64XX Driver; if not, write to the Free Software # along with 88SE64XX/88SE94XX Driver; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
# #
config SCSI_MVSAS config SCSI_MVSAS
tristate "Marvell 88SE64XX SAS/SATA support" tristate "Marvell 88SE64XX/88SE94XX SAS/SATA support"
depends on PCI depends on PCI
select SCSI_SAS_LIBSAS select SCSI_SAS_LIBSAS
select FW_LOADER select FW_LOADER
help help
This driver supports Marvell's SAS/SATA 3Gb/s PCI-E 88SE64XX This driver supports Marvell's SAS/SATA 3Gb/s PCI-E 88SE64XX and 6Gb/s
chip based host adapters. PCI-E 88SE94XX chip based host adapters.
config SCSI_MVSAS_DEBUG
bool "Compile in debug mode"
default y
depends on SCSI_MVSAS
help
Compiles the 88SE64XX/88SE94XX driver in debug mode. In debug mode,
the driver prints some messages to the console.

9
drivers/scsi/mvsas/Makefile
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@ -1,5 +1,5 @@
# #
# Makefile for Marvell 88SE64xx SAS/SATA driver. # Makefile for Marvell 88SE64xx/88SE84xx SAS/SATA driver.
# #
# Copyright 2007 Red Hat, Inc. # Copyright 2007 Red Hat, Inc.
# Copyright 2008 Marvell. <kewei@marvell.com> # Copyright 2008 Marvell. <kewei@marvell.com>
@ -21,7 +21,12 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
# USA # USA
ifeq ($(CONFIG_SCSI_MVSAS_DEBUG),y)
EXTRA_CFLAGS += -DMV_DEBUG
endif
obj-$(CONFIG_SCSI_MVSAS) += mvsas.o obj-$(CONFIG_SCSI_MVSAS) += mvsas.o
mvsas-y += mv_init.o \ mvsas-y += mv_init.o \
mv_sas.o \ mv_sas.o \
mv_64xx.o mv_64xx.o \
mv_94xx.o

811
drivers/scsi/mvsas/mv_64xx.c
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@ -1,184 +1,793 @@
/* /*
mv_64xx.c - Marvell 88SE6440 SAS/SATA support * Marvell 88SE64xx hardware specific
*
Copyright 2007 Red Hat, Inc. * Copyright 2007 Red Hat, Inc.
Copyright 2008 Marvell. <kewei@marvell.com> * Copyright 2008 Marvell. <kewei@marvell.com>
*
This program is free software; you can redistribute it and/or * This file is licensed under GPLv2.
modify it under the terms of the GNU General Public License as *
published by the Free Software Foundation; either version 2, * This program is free software; you can redistribute it and/or
or (at your option) any later version. * modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
This program is distributed in the hope that it will be useful, * License.
but WITHOUT ANY WARRANTY; without even the implied warranty *
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * This program is distributed in the hope that it will be useful,
See the GNU General Public License for more details. * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
You should have received a copy of the GNU General Public * General Public License for more details.
License along with this program; see the file COPYING. If not, *
write to the Free Software Foundation, 675 Mass Ave, Cambridge, * You should have received a copy of the GNU General Public License
MA 02139, USA. * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
*/ * USA
*/
#include "mv_sas.h" #include "mv_sas.h"
#include "mv_64xx.h" #include "mv_64xx.h"
#include "mv_chips.h" #include "mv_chips.h"
void mvs_detect_porttype(struct mvs_info *mvi, int i) static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
u32 reg; u32 reg;
struct mvs_phy *phy = &mvi->phy[i]; struct mvs_phy *phy = &mvi->phy[i];
/* TODO check & save device type */ /* TODO check & save device type */
reg = mr32(GBL_PORT_TYPE); reg = mr32(MVS_GBL_PORT_TYPE);
phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
if (reg & MODE_SAS_SATA & (1 << i)) if (reg & MODE_SAS_SATA & (1 << i))
phy->phy_type |= PORT_TYPE_SAS; phy->phy_type |= PORT_TYPE_SAS;
else else
phy->phy_type |= PORT_TYPE_SATA; phy->phy_type |= PORT_TYPE_SATA;
} }
void mvs_enable_xmt(struct mvs_info *mvi, int PhyId) static void __devinit mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
u32 tmp; u32 tmp;
tmp = mr32(PCS); tmp = mr32(MVS_PCS);
if (mvi->chip->n_phy <= 4) if (mvi->chip->n_phy <= 4)
tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT); tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT);
else else
tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT2); tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
mw32(PCS, tmp); mw32(MVS_PCS, tmp);
} }
void __devinit mvs_phy_hacks(struct mvs_info *mvi) static void __devinit mvs_64xx_phy_hacks(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs;
mvs_phy_hacks(mvi);
if (!(mvi->flags & MVF_FLAG_SOC)) {
/* TEST - for phy decoding error, adjust voltage levels */
mw32(MVS_P0_VSR_ADDR + 0, 0x8);
mw32(MVS_P0_VSR_DATA + 0, 0x2F0);
mw32(MVS_P0_VSR_ADDR + 8, 0x8);
mw32(MVS_P0_VSR_DATA + 8, 0x2F0);
mw32(MVS_P0_VSR_ADDR + 16, 0x8);
mw32(MVS_P0_VSR_DATA + 16, 0x2F0);
mw32(MVS_P0_VSR_ADDR + 24, 0x8);
mw32(MVS_P0_VSR_DATA + 24, 0x2F0);
} else {
int i;
/* disable auto port detection */
mw32(MVS_GBL_PORT_TYPE, 0);
for (i = 0; i < mvi->chip->n_phy; i++) {
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7);
mvs_write_port_vsr_data(mvi, i, 0x90000000);
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9);
mvs_write_port_vsr_data(mvi, i, 0x50f2);
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11);
mvs_write_port_vsr_data(mvi, i, 0x0e);
}
}
}
static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id)
{
void __iomem *regs = mvi->regs;
u32 reg, tmp;
if (!(mvi->flags & MVF_FLAG_SOC)) {
if (phy_id < 4)
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &reg);
else
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &reg);
} else
reg = mr32(MVS_PHY_CTL);
tmp = reg;
if (phy_id < 4)
tmp |= (1U << phy_id) << PCTL_LINK_OFFS;
else
tmp |= (1U << (phy_id - 4)) << PCTL_LINK_OFFS;
if (!(mvi->flags & MVF_FLAG_SOC)) {
if (phy_id < 4) {
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
mdelay(10);
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg);
} else {
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
mdelay(10);
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg);
}
} else {
mw32(MVS_PHY_CTL, tmp);
mdelay(10);
mw32(MVS_PHY_CTL, reg);
}
}
static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
{
u32 tmp;
tmp = mvs_read_port_irq_stat(mvi, phy_id);
tmp &= ~PHYEV_RDY_CH;
mvs_write_port_irq_stat(mvi, phy_id, tmp);
tmp = mvs_read_phy_ctl(mvi, phy_id);
if (hard)
tmp |= PHY_RST_HARD;
else
tmp |= PHY_RST;
mvs_write_phy_ctl(mvi, phy_id, tmp);
if (hard) {
do {
tmp = mvs_read_phy_ctl(mvi, phy_id);
} while (tmp & PHY_RST_HARD);
}
}
static int __devinit mvs_64xx_chip_reset(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs;
u32 tmp;
int i;
/* make sure interrupts are masked immediately (paranoia) */
mw32(MVS_GBL_CTL, 0);
tmp = mr32(MVS_GBL_CTL);
/* Reset Controller */
if (!(tmp & HBA_RST)) {
if (mvi->flags & MVF_PHY_PWR_FIX) {
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
tmp &= ~PCTL_PWR_OFF;
tmp |= PCTL_PHY_DSBL;
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
tmp &= ~PCTL_PWR_OFF;
tmp |= PCTL_PHY_DSBL;
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
}
}
/* make sure interrupts are masked immediately (paranoia) */
mw32(MVS_GBL_CTL, 0);
tmp = mr32(MVS_GBL_CTL);
/* Reset Controller */
if (!(tmp & HBA_RST)) {
/* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
mw32_f(MVS_GBL_CTL, HBA_RST);
}
/* wait for reset to finish; timeout is just a guess */
i = 1000;
while (i-- > 0) {
msleep(10);
if (!(mr32(MVS_GBL_CTL) & HBA_RST))
break;
}
if (mr32(MVS_GBL_CTL) & HBA_RST) {
dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n");
return -EBUSY;
}
return 0;
}
static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
{
void __iomem *regs = mvi->regs;
u32 tmp;
if (!(mvi->flags & MVF_FLAG_SOC)) {
u32 offs;
if (phy_id < 4)
offs = PCR_PHY_CTL;
else {
offs = PCR_PHY_CTL2;
phy_id -= 4;
}
pci_read_config_dword(mvi->pdev, offs, &tmp);
tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
pci_write_config_dword(mvi->pdev, offs, tmp);
} else {
tmp = mr32(MVS_PHY_CTL);
tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id);
mw32(MVS_PHY_CTL, tmp);
}
}
static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
{
void __iomem *regs = mvi->regs;
u32 tmp;
if (!(mvi->flags & MVF_FLAG_SOC)) {
u32 offs;
if (phy_id < 4)
offs = PCR_PHY_CTL;
else {
offs = PCR_PHY_CTL2;
phy_id -= 4;
}
pci_read_config_dword(mvi->pdev, offs, &tmp);
tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
pci_write_config_dword(mvi->pdev, offs, tmp);
} else {
tmp = mr32(MVS_PHY_CTL);
tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id));
mw32(MVS_PHY_CTL, tmp);
}
}
static int __devinit mvs_64xx_init(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs;
int i;
u32 tmp, cctl;
if (mvi->pdev && mvi->pdev->revision == 0)
mvi->flags |= MVF_PHY_PWR_FIX;
if (!(mvi->flags & MVF_FLAG_SOC)) {
mvs_show_pcie_usage(mvi);
tmp = mvs_64xx_chip_reset(mvi);
if (tmp)
return tmp;
} else {
tmp = mr32(MVS_PHY_CTL);
tmp &= ~PCTL_PWR_OFF;
tmp |= PCTL_PHY_DSBL;
mw32(MVS_PHY_CTL, tmp);
}
/* Init Chip */
/* make sure RST is set; HBA_RST /should/ have done that for us */
cctl = mr32(MVS_CTL) & 0xFFFF;
if (cctl & CCTL_RST)
cctl &= ~CCTL_RST;
else
mw32_f(MVS_CTL, cctl | CCTL_RST);
if (!(mvi->flags & MVF_FLAG_SOC)) {
/* write to device control _AND_ device status register */
pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
tmp &= ~PRD_REQ_MASK;
tmp |= PRD_REQ_SIZE;
pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
tmp &= ~PCTL_PWR_OFF;
tmp &= ~PCTL_PHY_DSBL;
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
tmp &= PCTL_PWR_OFF;
tmp &= ~PCTL_PHY_DSBL;
pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
} else {
tmp = mr32(MVS_PHY_CTL);
tmp &= ~PCTL_PWR_OFF;
tmp |= PCTL_COM_ON;
tmp &= ~PCTL_PHY_DSBL;
tmp |= PCTL_LINK_RST;
mw32(MVS_PHY_CTL, tmp);
msleep(100);
tmp &= ~PCTL_LINK_RST;
mw32(MVS_PHY_CTL, tmp);
msleep(100);
}
/* reset control */
mw32(MVS_PCS, 0); /* MVS_PCS */
/* init phys */
mvs_64xx_phy_hacks(mvi);
/* enable auto port detection */
mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN);
mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
mw32(MVS_TX_LO, mvi->tx_dma);
mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
mw32(MVS_RX_LO, mvi->rx_dma);
mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
for (i = 0; i < mvi->chip->n_phy; i++) {
/* set phy local SAS address */
/* should set little endian SAS address to 64xx chip */
mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI,
cpu_to_be64(mvi->phy[i].dev_sas_addr));
mvs_64xx_enable_xmt(mvi, i);
mvs_64xx_phy_reset(mvi, i, 1);
msleep(500);
mvs_64xx_detect_porttype(mvi, i);
}
if (mvi->flags & MVF_FLAG_SOC) {
/* set select registers */
writel(0x0E008000, regs + 0x000);
writel(0x59000008, regs + 0x004);
writel(0x20, regs + 0x008);
writel(0x20, regs + 0x00c);
writel(0x20, regs + 0x010);
writel(0x20, regs + 0x014);
writel(0x20, regs + 0x018);
writel(0x20, regs + 0x01c);
}
for (i = 0; i < mvi->chip->n_phy; i++) {
/* clear phy int status */
tmp = mvs_read_port_irq_stat(mvi, i);
tmp &= ~PHYEV_SIG_FIS;
mvs_write_port_irq_stat(mvi, i, tmp);
/* set phy int mask */
tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR |
PHYEV_DEC_ERR;
mvs_write_port_irq_mask(mvi, i, tmp);
msleep(100);
mvs_update_phyinfo(mvi, i, 1);
}
/* FIXME: update wide port bitmaps */
/* little endian for open address and command table, etc. */
/*
* it seems that ( from the spec ) turning on big-endian won't
* do us any good on big-endian machines, need further confirmation
*/
cctl = mr32(MVS_CTL);
cctl |= CCTL_ENDIAN_CMD;
cctl |= CCTL_ENDIAN_DATA;
cctl &= ~CCTL_ENDIAN_OPEN;
cctl |= CCTL_ENDIAN_RSP;
mw32_f(MVS_CTL, cctl);
/* reset CMD queue */
tmp = mr32(MVS_PCS);
tmp |= PCS_CMD_RST;
mw32(MVS_PCS, tmp);
/* interrupt coalescing may cause missing HW interrput in some case,
* and the max count is 0x1ff, while our max slot is 0x200,
* it will make count 0.
*/
tmp = 0;
mw32(MVS_INT_COAL, tmp);
tmp = 0x100;
mw32(MVS_INT_COAL_TMOUT, tmp);
/* ladies and gentlemen, start your engines */
mw32(MVS_TX_CFG, 0);
mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
/* enable CMD/CMPL_Q/RESP mode */
mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN |
PCS_CMD_EN | PCS_CMD_STOP_ERR);
/* enable completion queue interrupt */
tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
CINT_DMA_PCIE);
mw32(MVS_INT_MASK, tmp);
/* Enable SRS interrupt */
mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
return 0;
}
static int mvs_64xx_ioremap(struct mvs_info *mvi)
{
if (!mvs_ioremap(mvi, 4, 2))
return 0;
return -1;
}
static void mvs_64xx_iounmap(struct mvs_info *mvi)
{
mvs_iounmap(mvi->regs);
mvs_iounmap(mvi->regs_ex);
}
static void mvs_64xx_interrupt_enable(struct mvs_info *mvi)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
u32 tmp; u32 tmp;
/* workaround for SATA R-ERR, to ignore phy glitch */ tmp = mr32(MVS_GBL_CTL);
tmp = mvs_cr32(regs, CMD_PHY_TIMER); mw32(MVS_GBL_CTL, tmp | INT_EN);
tmp &= ~(1 << 9);
tmp |= (1 << 10);
mvs_cw32(regs, CMD_PHY_TIMER, tmp);
/* enable retry 127 times */
mvs_cw32(regs, CMD_SAS_CTL1, 0x7f7f);
/* extend open frame timeout to max */
tmp = mvs_cr32(regs, CMD_SAS_CTL0);
tmp &= ~0xffff;
tmp |= 0x3fff;
mvs_cw32(regs, CMD_SAS_CTL0, tmp);
/* workaround for WDTIMEOUT , set to 550 ms */
mvs_cw32(regs, CMD_WD_TIMER, 0x86470);
/* not to halt for different port op during wideport link change */
mvs_cw32(regs, CMD_APP_ERR_CONFIG, 0xffefbf7d);
/* workaround for Seagate disk not-found OOB sequence, recv
* COMINIT before sending out COMWAKE */
tmp = mvs_cr32(regs, CMD_PHY_MODE_21);
tmp &= 0x0000ffff;
tmp |= 0x00fa0000;
mvs_cw32(regs, CMD_PHY_MODE_21, tmp);
tmp = mvs_cr32(regs, CMD_PHY_TIMER);
tmp &= 0x1fffffff;
tmp |= (2U << 29); /* 8 ms retry */
mvs_cw32(regs, CMD_PHY_TIMER, tmp);
/* TEST - for phy decoding error, adjust voltage levels */
mw32(P0_VSR_ADDR + 0, 0x8);
mw32(P0_VSR_DATA + 0, 0x2F0);
mw32(P0_VSR_ADDR + 8, 0x8);
mw32(P0_VSR_DATA + 8, 0x2F0);
mw32(P0_VSR_ADDR + 16, 0x8);
mw32(P0_VSR_DATA + 16, 0x2F0);
mw32(P0_VSR_ADDR + 24, 0x8);
mw32(P0_VSR_DATA + 24, 0x2F0);
} }
void mvs_hba_interrupt_enable(struct mvs_info *mvi) static void mvs_64xx_interrupt_disable(struct mvs_info *mvi)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
u32 tmp; u32 tmp;
tmp = mr32(GBL_CTL); tmp = mr32(MVS_GBL_CTL);
mw32(MVS_GBL_CTL, tmp & ~INT_EN);
mw32(GBL_CTL, tmp | INT_EN);
} }
void mvs_hba_interrupt_disable(struct mvs_info *mvi) static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq)
{
void __iomem *regs = mvi->regs;
u32 stat;
if (!(mvi->flags & MVF_FLAG_SOC)) {
stat = mr32(MVS_GBL_INT_STAT);
if (stat == 0 || stat == 0xffffffff)
return 0;
} else
stat = 1;
return stat;
}
static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat)
{
void __iomem *regs = mvi->regs;
/* clear CMD_CMPLT ASAP */
mw32_f(MVS_INT_STAT, CINT_DONE);
#ifndef MVS_USE_TASKLET
spin_lock(&mvi->lock);
#endif
mvs_int_full(mvi);
#ifndef MVS_USE_TASKLET
spin_unlock(&mvi->lock);
#endif
return IRQ_HANDLED;
}
static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx)
{
u32 tmp;
mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));
mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));
do {
tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));
} while (tmp & 1 << (slot_idx % 32));
do {
tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));
} while (tmp & 1 << (slot_idx % 32));
}
static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
u32 tfs)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
u32 tmp; u32 tmp;
tmp = mr32(GBL_CTL); if (type == PORT_TYPE_SATA) {
tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
mw32(GBL_CTL, tmp & ~INT_EN); mw32(MVS_INT_STAT_SRS_0, tmp);
}
mw32(MVS_INT_STAT, CINT_CI_STOP);
tmp = mr32(MVS_PCS) | 0xFF00;
mw32(MVS_PCS, tmp);
} }
void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port) static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
u32 tmp, offs; u32 tmp, offs;
u8 *tfs = &port->taskfileset;
if (*tfs == MVS_ID_NOT_MAPPED) if (*tfs == MVS_ID_NOT_MAPPED)
return; return;
offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT); offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
if (*tfs < 16) { if (*tfs < 16) {
tmp = mr32(PCS); tmp = mr32(MVS_PCS);
mw32(PCS, tmp & ~offs); mw32(MVS_PCS, tmp & ~offs);
} else { } else {
tmp = mr32(CTL); tmp = mr32(MVS_CTL);
mw32(CTL, tmp & ~offs); mw32(MVS_CTL, tmp & ~offs);
} }
tmp = mr32(INT_STAT_SRS) & (1U << *tfs); tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs);
if (tmp) if (tmp)
mw32(INT_STAT_SRS, tmp); mw32(MVS_INT_STAT_SRS_0, tmp);
*tfs = MVS_ID_NOT_MAPPED; *tfs = MVS_ID_NOT_MAPPED;
return;
} }
u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port) static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
{ {
int i; int i;
u32 tmp, offs; u32 tmp, offs;
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
if (port->taskfileset != MVS_ID_NOT_MAPPED) if (*tfs != MVS_ID_NOT_MAPPED)
return 0; return 0;
tmp = mr32(PCS); tmp = mr32(MVS_PCS);
for (i = 0; i < mvi->chip->srs_sz; i++) { for (i = 0; i < mvi->chip->srs_sz; i++) {
if (i == 16) if (i == 16)
tmp = mr32(CTL); tmp = mr32(MVS_CTL);
offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT); offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
if (!(tmp & offs)) { if (!(tmp & offs)) {
port->taskfileset = i; *tfs = i;
if (i < 16) if (i < 16)
mw32(PCS, tmp | offs); mw32(MVS_PCS, tmp | offs);
else else
mw32(CTL, tmp | offs); mw32(MVS_CTL, tmp | offs);
tmp = mr32(INT_STAT_SRS) & (1U << i); tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i);
if (tmp) if (tmp)
mw32(INT_STAT_SRS, tmp); mw32(MVS_INT_STAT_SRS_0, tmp);
return 0; return 0;
} }
} }
return MVS_ID_NOT_MAPPED; return MVS_ID_NOT_MAPPED;
} }
void mvs_64xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
{
int i;
struct scatterlist *sg;
struct mvs_prd *buf_prd = prd;
for_each_sg(scatter, sg, nr, i) {
buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
buf_prd->len = cpu_to_le32(sg_dma_len(sg));
buf_prd++;
}
}
static int mvs_64xx_oob_done(struct mvs_info *mvi, int i)
{
u32 phy_st;
mvs_write_port_cfg_addr(mvi, i,
PHYR_PHY_STAT);
phy_st = mvs_read_port_cfg_data(mvi, i);
if (phy_st & PHY_OOB_DTCTD)
return 1;
return 0;
}
static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i,
struct sas_identify_frame *id)
{
struct mvs_phy *phy = &mvi->phy[i];
struct asd_sas_phy *sas_phy = &phy->sas_phy;
sas_phy->linkrate =
(phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
phy->minimum_linkrate =
(phy->phy_status &
PHY_MIN_SPP_PHYS_LINK_RATE_MASK) >> 8;
phy->maximum_linkrate =
(phy->phy_status &
PHY_MAX_SPP_PHYS_LINK_RATE_MASK) >> 12;
mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
phy->dev_info = mvs_read_port_cfg_data(mvi, i);
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
phy->att_dev_sas_addr =
(u64) mvs_read_port_cfg_data(mvi, i) << 32;
mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
phy->att_dev_sas_addr = SAS_ADDR(&phy->att_dev_sas_addr);
}
static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i)
{
u32 tmp;
struct mvs_phy *phy = &mvi->phy[i];
/* workaround for HW phy decoding error on 1.5g disk drive */
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
tmp = mvs_read_port_vsr_data(mvi, i);
if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
SAS_LINK_RATE_1_5_GBPS)
tmp &= ~PHY_MODE6_LATECLK;
else
tmp |= PHY_MODE6_LATECLK;
mvs_write_port_vsr_data(mvi, i, tmp);
}
void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
struct sas_phy_linkrates *rates)
{
u32 lrmin = 0, lrmax = 0;
u32 tmp;
tmp = mvs_read_phy_ctl(mvi, phy_id);
lrmin = (rates->minimum_linkrate << 8);
lrmax = (rates->maximum_linkrate << 12);
if (lrmin) {
tmp &= ~(0xf << 8);
tmp |= lrmin;
}
if (lrmax) {
tmp &= ~(0xf << 12);
tmp |= lrmax;
}
mvs_write_phy_ctl(mvi, phy_id, tmp);
mvs_64xx_phy_reset(mvi, phy_id, 1);
}
static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi)
{
u32 tmp;
void __iomem *regs = mvi->regs;
tmp = mr32(MVS_PCS);
mw32(MVS_PCS, tmp & 0xFFFF);
mw32(MVS_PCS, tmp);
tmp = mr32(MVS_CTL);
mw32(MVS_CTL, tmp & 0xFFFF);
mw32(MVS_CTL, tmp);
}
u32 mvs_64xx_spi_read_data(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs_ex;
return ior32(SPI_DATA_REG_64XX);
}
void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data)
{
void __iomem *regs = mvi->regs_ex;
iow32(SPI_DATA_REG_64XX, data);
}
int mvs_64xx_spi_buildcmd(struct mvs_info *mvi,
u32 *dwCmd,
u8 cmd,
u8 read,
u8 length,
u32 addr
)
{
u32 dwTmp;
dwTmp = ((u32)cmd << 24) | ((u32)length << 19);
if (read)
dwTmp |= 1U<<23;
if (addr != MV_MAX_U32) {
dwTmp |= 1U<<22;
dwTmp |= (addr & 0x0003FFFF);
}
*dwCmd = dwTmp;
return 0;
}
int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
{
void __iomem *regs = mvi->regs_ex;
int retry;
for (retry = 0; retry < 1; retry++) {
iow32(SPI_CTRL_REG_64XX, SPI_CTRL_VENDOR_ENABLE);
iow32(SPI_CMD_REG_64XX, cmd);
iow32(SPI_CTRL_REG_64XX,
SPI_CTRL_VENDOR_ENABLE | SPI_CTRL_SPISTART);
}
return 0;
}
int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
{
void __iomem *regs = mvi->regs_ex;
u32 i, dwTmp;
for (i = 0; i < timeout; i++) {
dwTmp = ior32(SPI_CTRL_REG_64XX);
if (!(dwTmp & SPI_CTRL_SPISTART))
return 0;
msleep(10);
}
return -1;
}
#ifndef DISABLE_HOTPLUG_DMA_FIX
void mvs_64xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
{
int i;
struct mvs_prd *buf_prd = prd;
buf_prd += from;
for (i = 0; i < MAX_SG_ENTRY - from; i++) {
buf_prd->addr = cpu_to_le64(buf_dma);
buf_prd->len = cpu_to_le32(buf_len);
++buf_prd;
}
}
#endif
const struct mvs_dispatch mvs_64xx_dispatch = {
"mv64xx",
mvs_64xx_init,
NULL,
mvs_64xx_ioremap,
mvs_64xx_iounmap,
mvs_64xx_isr,
mvs_64xx_isr_status,
mvs_64xx_interrupt_enable,
mvs_64xx_interrupt_disable,
mvs_read_phy_ctl,
mvs_write_phy_ctl,
mvs_read_port_cfg_data,
mvs_write_port_cfg_data,
mvs_write_port_cfg_addr,
mvs_read_port_vsr_data,
mvs_write_port_vsr_data,
mvs_write_port_vsr_addr,
mvs_read_port_irq_stat,
mvs_write_port_irq_stat,
mvs_read_port_irq_mask,
mvs_write_port_irq_mask,
mvs_get_sas_addr,
mvs_64xx_command_active,
mvs_64xx_issue_stop,
mvs_start_delivery,
mvs_rx_update,
mvs_int_full,
mvs_64xx_assign_reg_set,
mvs_64xx_free_reg_set,
mvs_get_prd_size,
mvs_get_prd_count,
mvs_64xx_make_prd,
mvs_64xx_detect_porttype,
mvs_64xx_oob_done,
mvs_64xx_fix_phy_info,
mvs_64xx_phy_work_around,
mvs_64xx_phy_set_link_rate,
mvs_hw_max_link_rate,
mvs_64xx_phy_disable,
mvs_64xx_phy_enable,
mvs_64xx_phy_reset,
mvs_64xx_stp_reset,
mvs_64xx_clear_active_cmds,
mvs_64xx_spi_read_data,
mvs_64xx_spi_write_data,
mvs_64xx_spi_buildcmd,
mvs_64xx_spi_issuecmd,
mvs_64xx_spi_waitdataready,
#ifndef DISABLE_HOTPLUG_DMA_FIX
mvs_64xx_fix_dma,
#endif
};

75
drivers/scsi/mvsas/mv_64xx.h
View File

@ -1,11 +1,43 @@
/*
* Marvell 88SE64xx hardware specific head file
*
* Copyright 2007 Red Hat, Inc.
* Copyright 2008 Marvell. <kewei@marvell.com>
*
* This file is licensed under GPLv2.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*/
#ifndef _MVS64XX_REG_H_ #ifndef _MVS64XX_REG_H_
#define _MVS64XX_REG_H_ #define _MVS64XX_REG_H_
#include <linux/types.h>
#define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS
/* enhanced mode registers (BAR4) */ /* enhanced mode registers (BAR4) */
enum hw_registers { enum hw_registers {
MVS_GBL_CTL = 0x04, /* global control */ MVS_GBL_CTL = 0x04, /* global control */
MVS_GBL_INT_STAT = 0x08, /* global irq status */ MVS_GBL_INT_STAT = 0x08, /* global irq status */
MVS_GBL_PI = 0x0C, /* ports implemented bitmask */ MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
MVS_PHY_CTL = 0x40, /* SOC PHY Control */
MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
MVS_GBL_PORT_TYPE = 0xa0, /* port type */ MVS_GBL_PORT_TYPE = 0xa0, /* port type */
MVS_CTL = 0x100, /* SAS/SATA port configuration */ MVS_CTL = 0x100, /* SAS/SATA port configuration */
@ -30,17 +62,19 @@ enum hw_registers {
MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */ MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
MVS_INT_STAT = 0x150, /* Central int status */ MVS_INT_STAT = 0x150, /* Central int status */
MVS_INT_MASK = 0x154, /* Central int enable */ MVS_INT_MASK = 0x154, /* Central int enable */
MVS_INT_STAT_SRS = 0x158, /* SATA register set status */ MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
MVS_INT_MASK_SRS = 0x15C, MVS_INT_MASK_SRS_0 = 0x15C,
/* ports 1-3 follow after this */ /* ports 1-3 follow after this */
MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */ MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */ MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
MVS_P4_INT_STAT = 0x200, /* Port 4 interrupt status */ /* ports 5-7 follow after this */
MVS_P4_INT_MASK = 0x204, /* Port 4 interrupt enable mask */ MVS_P4_INT_STAT = 0x200, /* Port4 interrupt status */
MVS_P4_INT_MASK = 0x204, /* Port4 interrupt enable mask */
/* ports 1-3 follow after this */ /* ports 1-3 follow after this */
MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */ MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
/* ports 5-7 follow after this */
MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */ MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */ MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
@ -49,20 +83,23 @@ enum hw_registers {
/* ports 1-3 follow after this */ /* ports 1-3 follow after this */
MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */ MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */ MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
MVS_P4_CFG_ADDR = 0x230, /* Port 4 config address */ /* ports 5-7 follow after this */
MVS_P4_CFG_DATA = 0x234, /* Port 4 config data */ MVS_P4_CFG_ADDR = 0x230, /* Port4 config address */
MVS_P4_CFG_DATA = 0x234, /* Port4 config data */
/* ports 1-3 follow after this */ /* ports 1-3 follow after this */
MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */ MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */ MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
MVS_P4_VSR_ADDR = 0x250, /* port 4 VSR addr */ /* ports 5-7 follow after this */
MVS_P4_VSR_DATA = 0x254, /* port 4 VSR data */ MVS_P4_VSR_ADDR = 0x250, /* port4 VSR addr */
MVS_P4_VSR_DATA = 0x254, /* port4 VSR data */
}; };
enum pci_cfg_registers { enum pci_cfg_registers {
PCR_PHY_CTL = 0x40, PCR_PHY_CTL = 0x40,
PCR_PHY_CTL2 = 0x90, PCR_PHY_CTL2 = 0x90,
PCR_DEV_CTRL = 0xE8, PCR_DEV_CTRL = 0xE8,
PCR_LINK_STAT = 0xF2,
}; };
/* SAS/SATA Vendor Specific Port Registers */ /* SAS/SATA Vendor Specific Port Registers */
@ -83,10 +120,32 @@ enum sas_sata_vsp_regs {
VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */ VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
}; };
enum chip_register_bits {
PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
(0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
};
#define MAX_SG_ENTRY 64
struct mvs_prd { struct mvs_prd {
__le64 addr; /* 64-bit buffer address */ __le64 addr; /* 64-bit buffer address */
__le32 reserved; __le32 reserved;
__le32 len; /* 16-bit length */ __le32 len; /* 16-bit length */
}; };
#define SPI_CTRL_REG 0xc0
#define SPI_CTRL_VENDOR_ENABLE (1U<<29)
#define SPI_CTRL_SPIRDY (1U<<22)
#define SPI_CTRL_SPISTART (1U<<20)
#define SPI_CMD_REG 0xc4
#define SPI_DATA_REG 0xc8
#define SPI_CTRL_REG_64XX 0x10
#define SPI_CMD_REG_64XX 0x14
#define SPI_DATA_REG_64XX 0x18
#endif #endif

672
drivers/scsi/mvsas/mv_94xx.c Normal file
View File

@ -0,0 +1,672 @@
/*
* Marvell 88SE94xx hardware specific
*
* Copyright 2007 Red Hat, Inc.
* Copyright 2008 Marvell. <kewei@marvell.com>
*
* This file is licensed under GPLv2.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*/
#include "mv_sas.h"
#include "mv_94xx.h"
#include "mv_chips.h"
static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
{
u32 reg;
struct mvs_phy *phy = &mvi->phy[i];
u32 phy_status;
mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);
reg = mvs_read_port_vsr_data(mvi, i);
phy_status = ((reg & 0x3f0000) >> 16) & 0xff;
phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
switch (phy_status) {
case 0x10:
phy->phy_type |= PORT_TYPE_SAS;
break;
case 0x1d:
default:
phy->phy_type |= PORT_TYPE_SATA;
break;
}
}
static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
{
void __iomem *regs = mvi->regs;
u32 tmp;
tmp = mr32(MVS_PCS);
tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2);
mw32(MVS_PCS, tmp);
}
static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)
{
u32 tmp;
tmp = mvs_read_port_irq_stat(mvi, phy_id);
tmp &= ~PHYEV_RDY_CH;
mvs_write_port_irq_stat(mvi, phy_id, tmp);
if (hard) {
tmp = mvs_read_phy_ctl(mvi, phy_id);
tmp |= PHY_RST_HARD;
mvs_write_phy_ctl(mvi, phy_id, tmp);
do {
tmp = mvs_read_phy_ctl(mvi, phy_id);
} while (tmp & PHY_RST_HARD);
} else {
mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_STAT);
tmp = mvs_read_port_vsr_data(mvi, phy_id);
tmp |= PHY_RST;
mvs_write_port_vsr_data(mvi, phy_id, tmp);
}
}
static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
{
u32 tmp;
mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
tmp = mvs_read_port_vsr_data(mvi, phy_id);
mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);
}
static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
{
mvs_write_port_vsr_addr(mvi, phy_id, 0x1B4);
mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
mvs_write_port_vsr_addr(mvi, phy_id, 0x104);
mvs_write_port_vsr_data(mvi, phy_id, 0x00018080);
mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
mvs_write_port_vsr_data(mvi, phy_id, 0x00207fff);
}
static int __devinit mvs_94xx_init(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs;
int i;
u32 tmp, cctl;
mvs_show_pcie_usage(mvi);
if (mvi->flags & MVF_FLAG_SOC) {
tmp = mr32(MVS_PHY_CTL);
tmp &= ~PCTL_PWR_OFF;
tmp |= PCTL_PHY_DSBL;
mw32(MVS_PHY_CTL, tmp);
}
/* Init Chip */
/* make sure RST is set; HBA_RST /should/ have done that for us */
cctl = mr32(MVS_CTL) & 0xFFFF;
if (cctl & CCTL_RST)
cctl &= ~CCTL_RST;
else
mw32_f(MVS_CTL, cctl | CCTL_RST);
if (mvi->flags & MVF_FLAG_SOC) {
tmp = mr32(MVS_PHY_CTL);
tmp &= ~PCTL_PWR_OFF;
tmp |= PCTL_COM_ON;
tmp &= ~PCTL_PHY_DSBL;
tmp |= PCTL_LINK_RST;
mw32(MVS_PHY_CTL, tmp);
msleep(100);
tmp &= ~PCTL_LINK_RST;
mw32(MVS_PHY_CTL, tmp);
msleep(100);
}
/* reset control */
mw32(MVS_PCS, 0); /* MVS_PCS */
mw32(MVS_STP_REG_SET_0, 0);
mw32(MVS_STP_REG_SET_1, 0);
/* init phys */
mvs_phy_hacks(mvi);
/* disable Multiplexing, enable phy implemented */
mw32(MVS_PORTS_IMP, 0xFF);
mw32(MVS_PA_VSR_ADDR, 0x00000104);
mw32(MVS_PA_VSR_PORT, 0x00018080);
mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE8);
mw32(MVS_PA_VSR_PORT, 0x0084ffff);
/* set LED blink when IO*/
mw32(MVS_PA_VSR_ADDR, 0x00000030);
tmp = mr32(MVS_PA_VSR_PORT);
tmp &= 0xFFFF00FF;
tmp |= 0x00003300;
mw32(MVS_PA_VSR_PORT, tmp);
mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
mw32(MVS_TX_LO, mvi->tx_dma);
mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
mw32(MVS_RX_LO, mvi->rx_dma);
mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
for (i = 0; i < mvi->chip->n_phy; i++) {
mvs_94xx_phy_disable(mvi, i);
/* set phy local SAS address */
mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,
(mvi->phy[i].dev_sas_addr));
mvs_94xx_enable_xmt(mvi, i);
mvs_94xx_phy_enable(mvi, i);
mvs_94xx_phy_reset(mvi, i, 1);
msleep(500);
mvs_94xx_detect_porttype(mvi, i);
}
if (mvi->flags & MVF_FLAG_SOC) {
/* set select registers */
writel(0x0E008000, regs + 0x000);
writel(0x59000008, regs + 0x004);
writel(0x20, regs + 0x008);
writel(0x20, regs + 0x00c);
writel(0x20, regs + 0x010);
writel(0x20, regs + 0x014);
writel(0x20, regs + 0x018);
writel(0x20, regs + 0x01c);
}
for (i = 0; i < mvi->chip->n_phy; i++) {
/* clear phy int status */
tmp = mvs_read_port_irq_stat(mvi, i);
tmp &= ~PHYEV_SIG_FIS;
mvs_write_port_irq_stat(mvi, i, tmp);
/* set phy int mask */
tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH |
PHYEV_ID_DONE | PHYEV_DCDR_ERR | PHYEV_CRC_ERR ;
mvs_write_port_irq_mask(mvi, i, tmp);
msleep(100);
mvs_update_phyinfo(mvi, i, 1);
}
/* FIXME: update wide port bitmaps */
/* little endian for open address and command table, etc. */
/*
* it seems that ( from the spec ) turning on big-endian won't
* do us any good on big-endian machines, need further confirmation
*/
cctl = mr32(MVS_CTL);
cctl |= CCTL_ENDIAN_CMD;
cctl |= CCTL_ENDIAN_DATA;
cctl &= ~CCTL_ENDIAN_OPEN;
cctl |= CCTL_ENDIAN_RSP;
mw32_f(MVS_CTL, cctl);
/* reset CMD queue */
tmp = mr32(MVS_PCS);
tmp |= PCS_CMD_RST;
mw32(MVS_PCS, tmp);
/* interrupt coalescing may cause missing HW interrput in some case,
* and the max count is 0x1ff, while our max slot is 0x200,
* it will make count 0.
*/
tmp = 0;
mw32(MVS_INT_COAL, tmp);
tmp = 0x100;
mw32(MVS_INT_COAL_TMOUT, tmp);
/* ladies and gentlemen, start your engines */
mw32(MVS_TX_CFG, 0);
mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
/* enable CMD/CMPL_Q/RESP mode */
mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |
PCS_CMD_EN | PCS_CMD_STOP_ERR);
/* enable completion queue interrupt */
tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP |
CINT_DMA_PCIE);
tmp |= CINT_PHY_MASK;
mw32(MVS_INT_MASK, tmp);
/* Enable SRS interrupt */
mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
return 0;
}
static int mvs_94xx_ioremap(struct mvs_info *mvi)
{
if (!mvs_ioremap(mvi, 2, -1)) {
mvi->regs_ex = mvi->regs + 0x10200;
mvi->regs += 0x20000;
if (mvi->id == 1)
mvi->regs += 0x4000;
return 0;
}
return -1;
}
static void mvs_94xx_iounmap(struct mvs_info *mvi)
{
if (mvi->regs) {
mvi->regs -= 0x20000;
if (mvi->id == 1)
mvi->regs -= 0x4000;
mvs_iounmap(mvi->regs);
}
}
static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs_ex;
u32 tmp;
tmp = mr32(MVS_GBL_CTL);
tmp |= (IRQ_SAS_A | IRQ_SAS_B);
mw32(MVS_GBL_INT_STAT, tmp);
writel(tmp, regs + 0x0C);
writel(tmp, regs + 0x10);
writel(tmp, regs + 0x14);
writel(tmp, regs + 0x18);
mw32(MVS_GBL_CTL, tmp);
}
static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs_ex;
u32 tmp;
tmp = mr32(MVS_GBL_CTL);
tmp &= ~(IRQ_SAS_A | IRQ_SAS_B);
mw32(MVS_GBL_INT_STAT, tmp);
writel(tmp, regs + 0x0C);
writel(tmp, regs + 0x10);
writel(tmp, regs + 0x14);
writel(tmp, regs + 0x18);
mw32(MVS_GBL_CTL, tmp);
}
static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)
{
void __iomem *regs = mvi->regs_ex;
u32 stat = 0;
if (!(mvi->flags & MVF_FLAG_SOC)) {
stat = mr32(MVS_GBL_INT_STAT);
if (!(stat & (IRQ_SAS_A | IRQ_SAS_B)))
return 0;
}
return stat;
}
static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)
{
void __iomem *regs = mvi->regs;
if (((stat & IRQ_SAS_A) && mvi->id == 0) ||
((stat & IRQ_SAS_B) && mvi->id == 1)) {
mw32_f(MVS_INT_STAT, CINT_DONE);
#ifndef MVS_USE_TASKLET
spin_lock(&mvi->lock);
#endif
mvs_int_full(mvi);
#ifndef MVS_USE_TASKLET
spin_unlock(&mvi->lock);
#endif
}
return IRQ_HANDLED;
}
static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)
{
u32 tmp;
mvs_cw32(mvi, 0x300 + (slot_idx >> 3), 1 << (slot_idx % 32));
do {
tmp = mvs_cr32(mvi, 0x300 + (slot_idx >> 3));
} while (tmp & 1 << (slot_idx % 32));
}
static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,
u32 tfs)
{
void __iomem *regs = mvi->regs;
u32 tmp;
if (type == PORT_TYPE_SATA) {
tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs);
mw32(MVS_INT_STAT_SRS_0, tmp);
}
mw32(MVS_INT_STAT, CINT_CI_STOP);
tmp = mr32(MVS_PCS) | 0xFF00;
mw32(MVS_PCS, tmp);
}
static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)
{
void __iomem *regs = mvi->regs;
u32 tmp;
u8 reg_set = *tfs;
if (*tfs == MVS_ID_NOT_MAPPED)
return;
mvi->sata_reg_set &= ~bit(reg_set);
if (reg_set < 32) {
w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);
tmp = mr32(MVS_INT_STAT_SRS_0) & (u32)mvi->sata_reg_set;
if (tmp)
mw32(MVS_INT_STAT_SRS_0, tmp);
} else {
w_reg_set_enable(reg_set, mvi->sata_reg_set);
tmp = mr32(MVS_INT_STAT_SRS_1) & mvi->sata_reg_set;
if (tmp)
mw32(MVS_INT_STAT_SRS_1, tmp);
}
*tfs = MVS_ID_NOT_MAPPED;
return;
}
static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)
{
int i;
void __iomem *regs = mvi->regs;
if (*tfs != MVS_ID_NOT_MAPPED)
return 0;
i = mv_ffc64(mvi->sata_reg_set);
if (i > 32) {
mvi->sata_reg_set |= bit(i);
w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));
*tfs = i;
return 0;
} else if (i >= 0) {
mvi->sata_reg_set |= bit(i);
w_reg_set_enable(i, (u32)mvi->sata_reg_set);
*tfs = i;
return 0;
}
return MVS_ID_NOT_MAPPED;
}
static void mvs_94xx_make_prd(struct scatterlist *scatter, int nr, void *prd)
{
int i;
struct scatterlist *sg;
struct mvs_prd *buf_prd = prd;
for_each_sg(scatter, sg, nr, i) {
buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
buf_prd++;
}
}
static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)
{
u32 phy_st;
phy_st = mvs_read_phy_ctl(mvi, i);
if (phy_st & PHY_READY_MASK) /* phy ready */
return 1;
return 0;
}
static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,
struct sas_identify_frame *id)
{
int i;
u32 id_frame[7];
for (i = 0; i < 7; i++) {
mvs_write_port_cfg_addr(mvi, port_id,
CONFIG_ID_FRAME0 + i * 4);
id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
}
memcpy(id, id_frame, 28);
}
static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,
struct sas_identify_frame *id)
{
int i;
u32 id_frame[7];
/* mvs_hexdump(28, (u8 *)id_frame, 0); */
for (i = 0; i < 7; i++) {
mvs_write_port_cfg_addr(mvi, port_id,
CONFIG_ATT_ID_FRAME0 + i * 4);
id_frame[i] = mvs_read_port_cfg_data(mvi, port_id);
mv_dprintk("94xx phy %d atta frame %d %x.\n",
port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);
}
/* mvs_hexdump(28, (u8 *)id_frame, 0); */
memcpy(id, id_frame, 28);
}
static u32 mvs_94xx_make_dev_info(struct sas_identify_frame *id)
{
u32 att_dev_info = 0;
att_dev_info |= id->dev_type;
if (id->stp_iport)
att_dev_info |= PORT_DEV_STP_INIT;
if (id->smp_iport)
att_dev_info |= PORT_DEV_SMP_INIT;
if (id->ssp_iport)
att_dev_info |= PORT_DEV_SSP_INIT;
if (id->stp_tport)
att_dev_info |= PORT_DEV_STP_TRGT;
if (id->smp_tport)
att_dev_info |= PORT_DEV_SMP_TRGT;
if (id->ssp_tport)
att_dev_info |= PORT_DEV_SSP_TRGT;
att_dev_info |= (u32)id->phy_id<<24;
return att_dev_info;
}
static u32 mvs_94xx_make_att_info(struct sas_identify_frame *id)
{
return mvs_94xx_make_dev_info(id);
}
static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,
struct sas_identify_frame *id)
{
struct mvs_phy *phy = &mvi->phy[i];
struct asd_sas_phy *sas_phy = &phy->sas_phy;
mv_dprintk("get all reg link rate is 0x%x\n", phy->phy_status);
sas_phy->linkrate =
(phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
sas_phy->linkrate += 0x8;
mv_dprintk("get link rate is %d\n", sas_phy->linkrate);
phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
mvs_94xx_get_dev_identify_frame(mvi, i, id);
phy->dev_info = mvs_94xx_make_dev_info(id);
if (phy->phy_type & PORT_TYPE_SAS) {
mvs_94xx_get_att_identify_frame(mvi, i, id);
phy->att_dev_info = mvs_94xx_make_att_info(id);
phy->att_dev_sas_addr = *(u64 *)id->sas_addr;
} else {
phy->att_dev_info = PORT_DEV_STP_TRGT | 1;
}
}
void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,
struct sas_phy_linkrates *rates)
{
/* TODO */
}
static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)
{
u32 tmp;
void __iomem *regs = mvi->regs;
tmp = mr32(MVS_STP_REG_SET_0);
mw32(MVS_STP_REG_SET_0, 0);
mw32(MVS_STP_REG_SET_0, tmp);
tmp = mr32(MVS_STP_REG_SET_1);
mw32(MVS_STP_REG_SET_1, 0);
mw32(MVS_STP_REG_SET_1, tmp);
}
u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs_ex - 0x10200;
return mr32(SPI_RD_DATA_REG_94XX);
}
void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)
{
void __iomem *regs = mvi->regs_ex - 0x10200;
mw32(SPI_RD_DATA_REG_94XX, data);
}
int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,
u32 *dwCmd,
u8 cmd,
u8 read,
u8 length,
u32 addr
)
{
void __iomem *regs = mvi->regs_ex - 0x10200;
u32 dwTmp;
dwTmp = ((u32)cmd << 8) | ((u32)length << 4);
if (read)
dwTmp |= SPI_CTRL_READ_94XX;
if (addr != MV_MAX_U32) {
mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));
dwTmp |= SPI_ADDR_VLD_94XX;
}
*dwCmd = dwTmp;
return 0;
}
int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)
{
void __iomem *regs = mvi->regs_ex - 0x10200;
mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
return 0;
}
int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)
{
void __iomem *regs = mvi->regs_ex - 0x10200;
u32 i, dwTmp;
for (i = 0; i < timeout; i++) {
dwTmp = mr32(SPI_CTRL_REG_94XX);
if (!(dwTmp & SPI_CTRL_SpiStart_94XX))
return 0;
msleep(10);
}
return -1;
}
#ifndef DISABLE_HOTPLUG_DMA_FIX
void mvs_94xx_fix_dma(dma_addr_t buf_dma, int buf_len, int from, void *prd)
{
int i;
struct mvs_prd *buf_prd = prd;
buf_prd += from;
for (i = 0; i < MAX_SG_ENTRY - from; i++) {
buf_prd->addr = cpu_to_le64(buf_dma);
buf_prd->im_len.len = cpu_to_le32(buf_len);
++buf_prd;
}
}
#endif
const struct mvs_dispatch mvs_94xx_dispatch = {
"mv94xx",
mvs_94xx_init,
NULL,
mvs_94xx_ioremap,
mvs_94xx_iounmap,
mvs_94xx_isr,
mvs_94xx_isr_status,
mvs_94xx_interrupt_enable,
mvs_94xx_interrupt_disable,
mvs_read_phy_ctl,
mvs_write_phy_ctl,
mvs_read_port_cfg_data,
mvs_write_port_cfg_data,
mvs_write_port_cfg_addr,
mvs_read_port_vsr_data,
mvs_write_port_vsr_data,
mvs_write_port_vsr_addr,
mvs_read_port_irq_stat,
mvs_write_port_irq_stat,
mvs_read_port_irq_mask,
mvs_write_port_irq_mask,
mvs_get_sas_addr,
mvs_94xx_command_active,
mvs_94xx_issue_stop,
mvs_start_delivery,
mvs_rx_update,
mvs_int_full,
mvs_94xx_assign_reg_set,
mvs_94xx_free_reg_set,
mvs_get_prd_size,
mvs_get_prd_count,
mvs_94xx_make_prd,
mvs_94xx_detect_porttype,
mvs_94xx_oob_done,
mvs_94xx_fix_phy_info,
NULL,
mvs_94xx_phy_set_link_rate,
mvs_hw_max_link_rate,
mvs_94xx_phy_disable,
mvs_94xx_phy_enable,
mvs_94xx_phy_reset,
NULL,
mvs_94xx_clear_active_cmds,
mvs_94xx_spi_read_data,
mvs_94xx_spi_write_data,
mvs_94xx_spi_buildcmd,
mvs_94xx_spi_issuecmd,
mvs_94xx_spi_waitdataready,
#ifndef DISABLE_HOTPLUG_DMA_FIX
mvs_94xx_fix_dma,
#endif
};

222
drivers/scsi/mvsas/mv_94xx.h Normal file
View File

@ -0,0 +1,222 @@
/*
* Marvell 88SE94xx hardware specific head file
*
* Copyright 2007 Red Hat, Inc.
* Copyright 2008 Marvell. <kewei@marvell.com>
*
* This file is licensed under GPLv2.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*/
#ifndef _MVS94XX_REG_H_
#define _MVS94XX_REG_H_
#include <linux/types.h>
#define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS
enum hw_registers {
MVS_GBL_CTL = 0x04, /* global control */
MVS_GBL_INT_STAT = 0x00, /* global irq status */
MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
MVS_PHY_CTL = 0x40, /* SOC PHY Control */
MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
MVS_GBL_PORT_TYPE = 0xa0, /* port type */
MVS_CTL = 0x100, /* SAS/SATA port configuration */
MVS_PCS = 0x104, /* SAS/SATA port control/status */
MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
MVS_CMD_LIST_HI = 0x10C,
MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
MVS_RX_FIS_HI = 0x114,
MVS_STP_REG_SET_0 = 0x118, /* STP/SATA Register Set Enable */
MVS_STP_REG_SET_1 = 0x11C,
MVS_TX_CFG = 0x120, /* TX configuration */
MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
MVS_TX_HI = 0x128,
MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
MVS_RX_CFG = 0x134, /* RX configuration */
MVS_RX_LO = 0x138, /* RX (completion) ring addr */
MVS_RX_HI = 0x13C,
MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
MVS_INT_COAL = 0x148, /* Int coalescing config */
MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
MVS_INT_STAT = 0x150, /* Central int status */
MVS_INT_MASK = 0x154, /* Central int enable */
MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */
MVS_INT_MASK_SRS_0 = 0x15C,
MVS_INT_STAT_SRS_1 = 0x160,
MVS_INT_MASK_SRS_1 = 0x164,
MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
MVS_NON_NCQ_ERR_1 = 0x16C,
MVS_CMD_ADDR = 0x170, /* Command register port (addr) */
MVS_CMD_DATA = 0x174, /* Command register port (data) */
MVS_MEM_PARITY_ERR = 0x178, /* Memory parity error */
/* ports 1-3 follow after this */
MVS_P0_INT_STAT = 0x180, /* port0 interrupt status */
MVS_P0_INT_MASK = 0x184, /* port0 interrupt mask */
/* ports 5-7 follow after this */
MVS_P4_INT_STAT = 0x1A0, /* Port4 interrupt status */
MVS_P4_INT_MASK = 0x1A4, /* Port4 interrupt enable mask */
/* ports 1-3 follow after this */
MVS_P0_SER_CTLSTAT = 0x1D0, /* port0 serial control/status */
/* ports 5-7 follow after this */
MVS_P4_SER_CTLSTAT = 0x1E0, /* port4 serial control/status */
/* ports 1-3 follow after this */
MVS_P0_CFG_ADDR = 0x200, /* port0 phy register address */
MVS_P0_CFG_DATA = 0x204, /* port0 phy register data */
/* ports 5-7 follow after this */
MVS_P4_CFG_ADDR = 0x220, /* Port4 config address */
MVS_P4_CFG_DATA = 0x224, /* Port4 config data */
/* phys 1-3 follow after this */
MVS_P0_VSR_ADDR = 0x250, /* phy0 VSR address */
MVS_P0_VSR_DATA = 0x254, /* phy0 VSR data */
/* phys 1-3 follow after this */
/* multiplexing */
MVS_P4_VSR_ADDR = 0x250, /* phy4 VSR address */
MVS_P4_VSR_DATA = 0x254, /* phy4 VSR data */
MVS_PA_VSR_ADDR = 0x290, /* All port VSR addr */
MVS_PA_VSR_PORT = 0x294, /* All port VSR data */
};
enum pci_cfg_registers {
PCR_PHY_CTL = 0x40,
PCR_PHY_CTL2 = 0x90,
PCR_DEV_CTRL = 0x78,
PCR_LINK_STAT = 0x82,
};
/* SAS/SATA Vendor Specific Port Registers */
enum sas_sata_vsp_regs {
VSR_PHY_STAT = 0x00 * 4, /* Phy Status */
VSR_PHY_MODE1 = 0x01 * 4, /* phy tx */
VSR_PHY_MODE2 = 0x02 * 4, /* tx scc */
VSR_PHY_MODE3 = 0x03 * 4, /* pll */
VSR_PHY_MODE4 = 0x04 * 4, /* VCO */
VSR_PHY_MODE5 = 0x05 * 4, /* Rx */
VSR_PHY_MODE6 = 0x06 * 4, /* CDR */
VSR_PHY_MODE7 = 0x07 * 4, /* Impedance */
VSR_PHY_MODE8 = 0x08 * 4, /* Voltage */
VSR_PHY_MODE9 = 0x09 * 4, /* Test */
VSR_PHY_MODE10 = 0x0A * 4, /* Power */
VSR_PHY_MODE11 = 0x0B * 4, /* Phy Mode */
VSR_PHY_VS0 = 0x0C * 4, /* Vednor Specific 0 */
VSR_PHY_VS1 = 0x0D * 4, /* Vednor Specific 1 */
};
enum chip_register_bits {
PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (12),
PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
(0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
};
enum pci_interrupt_cause {
/* MAIN_IRQ_CAUSE (R10200) Bits*/
IRQ_COM_IN_I2O_IOP0 = (1 << 0),
IRQ_COM_IN_I2O_IOP1 = (1 << 1),
IRQ_COM_IN_I2O_IOP2 = (1 << 2),
IRQ_COM_IN_I2O_IOP3 = (1 << 3),
IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
IRQ_PCIF_DRBL0 = (1 << 12),
IRQ_PCIF_DRBL1 = (1 << 13),
IRQ_PCIF_DRBL2 = (1 << 14),
IRQ_PCIF_DRBL3 = (1 << 15),
IRQ_XOR_A = (1 << 16),
IRQ_XOR_B = (1 << 17),
IRQ_SAS_A = (1 << 18),
IRQ_SAS_B = (1 << 19),
IRQ_CPU_CNTRL = (1 << 20),
IRQ_GPIO = (1 << 21),
IRQ_UART = (1 << 22),
IRQ_SPI = (1 << 23),
IRQ_I2C = (1 << 24),
IRQ_SGPIO = (1 << 25),
IRQ_COM_ERR = (1 << 29),
IRQ_I2O_ERR = (1 << 30),
IRQ_PCIE_ERR = (1 << 31),
};
#define MAX_SG_ENTRY 255
struct mvs_prd_imt {
__le32 len:22;
u8 _r_a:2;
u8 misc_ctl:4;
u8 inter_sel:4;
};
struct mvs_prd {
/* 64-bit buffer address */
__le64 addr;
/* 22-bit length */
struct mvs_prd_imt im_len;
} __attribute__ ((packed));
#define SPI_CTRL_REG_94XX 0xc800
#define SPI_ADDR_REG_94XX 0xc804
#define SPI_WR_DATA_REG_94XX 0xc808
#define SPI_RD_DATA_REG_94XX 0xc80c
#define SPI_CTRL_READ_94XX (1U << 2)
#define SPI_ADDR_VLD_94XX (1U << 1)
#define SPI_CTRL_SpiStart_94XX (1U << 0)
#define mv_ffc(x) ffz(x)
static inline int
mv_ffc64(u64 v)
{
int i;
i = mv_ffc((u32)v);
if (i >= 0)
return i;
i = mv_ffc((u32)(v>>32));
if (i != 0)
return 32 + i;
return -1;
}
#define r_reg_set_enable(i) \
(((i) > 31) ? mr32(MVS_STP_REG_SET_1) : \
mr32(MVS_STP_REG_SET_0))
#define w_reg_set_enable(i, tmp) \
(((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
mw32(MVS_STP_REG_SET_0, tmp))
extern const struct mvs_dispatch mvs_94xx_dispatch;
#endif

212
drivers/scsi/mvsas/mv_chips.h
View File

@ -1,46 +1,81 @@
/*
* Marvell 88SE64xx/88SE94xx register IO interface
*
* Copyright 2007 Red Hat, Inc.
* Copyright 2008 Marvell. <kewei@marvell.com>
*
* This file is licensed under GPLv2.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*/
#ifndef _MV_CHIPS_H_ #ifndef _MV_CHIPS_H_
#define _MV_CHIPS_H_ #define _MV_CHIPS_H_
#define mr32(reg) readl(regs + MVS_##reg) #define mr32(reg) readl(regs + reg)
#define mw32(reg,val) writel((val), regs + MVS_##reg) #define mw32(reg, val) writel((val), regs + reg)
#define mw32_f(reg,val) do { \ #define mw32_f(reg, val) do { \
writel((val), regs + MVS_##reg); \ mw32(reg, val); \
readl(regs + MVS_##reg); \ mr32(reg); \
} while (0) } while (0)
static inline u32 mvs_cr32(void __iomem *regs, u32 addr) #define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
#define ior32(reg) inl((unsigned long)(regs + reg))
#define iow16(reg, val) outw((unsigned long)(val, regs + reg))
#define ior16(reg) inw((unsigned long)(regs + reg))
#define iow8(reg, val) outb((unsigned long)(val, regs + reg))
#define ior8(reg) inb((unsigned long)(regs + reg))
static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
{ {
mw32(CMD_ADDR, addr); void __iomem *regs = mvi->regs;
return mr32(CMD_DATA); mw32(MVS_CMD_ADDR, addr);
return mr32(MVS_CMD_DATA);
} }
static inline void mvs_cw32(void __iomem *regs, u32 addr, u32 val) static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
{ {
mw32(CMD_ADDR, addr); void __iomem *regs = mvi->regs;
mw32(CMD_DATA, val); mw32(MVS_CMD_ADDR, addr);
mw32(MVS_CMD_DATA, val);
} }
static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port) static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4): return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
mr32(P4_SER_CTLSTAT + (port - 4) * 4); mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
} }
static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val) static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
{ {
void __iomem *regs = mvi->regs; void __iomem *regs = mvi->regs;
if (port < 4) if (port < 4)
mw32(P0_SER_CTLSTAT + port * 4, val); mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
else else
mw32(P4_SER_CTLSTAT + (port - 4) * 4, val); mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
} }
static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port) static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
u32 off2, u32 port)
{ {
void __iomem *regs = mvi->regs + off; void __iomem *regs = mvi->regs + off;
void __iomem *regs2 = mvi->regs + off2; void __iomem *regs2 = mvi->regs + off2;
return (port < 4)?readl(regs + port * 8): return (port < 4) ? readl(regs + port * 8) :
readl(regs2 + (port - 4) * 8); readl(regs2 + (port - 4) * 8);
} }
@ -61,16 +96,19 @@ static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
MVS_P4_CFG_DATA, port); MVS_P4_CFG_DATA, port);
} }
static inline void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val) static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
u32 port, u32 val)
{ {
mvs_write_port(mvi, MVS_P0_CFG_DATA, mvs_write_port(mvi, MVS_P0_CFG_DATA,
MVS_P4_CFG_DATA, port, val); MVS_P4_CFG_DATA, port, val);
} }
static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr) static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
u32 port, u32 addr)
{ {
mvs_write_port(mvi, MVS_P0_CFG_ADDR, mvs_write_port(mvi, MVS_P0_CFG_ADDR,
MVS_P4_CFG_ADDR, port, addr); MVS_P4_CFG_ADDR, port, addr);
mdelay(10);
} }
static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port) static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
@ -79,16 +117,19 @@ static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
MVS_P4_VSR_DATA, port); MVS_P4_VSR_DATA, port);
} }
static inline void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val) static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
u32 port, u32 val)
{ {
mvs_write_port(mvi, MVS_P0_VSR_DATA, mvs_write_port(mvi, MVS_P0_VSR_DATA,
MVS_P4_VSR_DATA, port, val); MVS_P4_VSR_DATA, port, val);
} }
static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr) static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
u32 port, u32 addr)
{ {
mvs_write_port(mvi, MVS_P0_VSR_ADDR, mvs_write_port(mvi, MVS_P0_VSR_ADDR,
MVS_P4_VSR_ADDR, port, addr); MVS_P4_VSR_ADDR, port, addr);
mdelay(10);
} }
static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port) static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
@ -97,7 +138,8 @@ static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
MVS_P4_INT_STAT, port); MVS_P4_INT_STAT, port);
} }
static inline void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val) static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
u32 port, u32 val)
{ {
mvs_write_port(mvi, MVS_P0_INT_STAT, mvs_write_port(mvi, MVS_P0_INT_STAT,
MVS_P4_INT_STAT, port, val); MVS_P4_INT_STAT, port, val);
@ -107,12 +149,132 @@ static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
{ {
return mvs_read_port(mvi, MVS_P0_INT_MASK, return mvs_read_port(mvi, MVS_P0_INT_MASK,
MVS_P4_INT_MASK, port); MVS_P4_INT_MASK, port);
} }
static inline void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val) static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
u32 port, u32 val)
{ {
mvs_write_port(mvi, MVS_P0_INT_MASK, mvs_write_port(mvi, MVS_P0_INT_MASK,
MVS_P4_INT_MASK, port, val); MVS_P4_INT_MASK, port, val);
} }
#endif static inline void __devinit mvs_phy_hacks(struct mvs_info *mvi)
{
u32 tmp;
/* workaround for SATA R-ERR, to ignore phy glitch */
tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
tmp &= ~(1 << 9);
tmp |= (1 << 10);
mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
/* enable retry 127 times */
mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
/* extend open frame timeout to max */
tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
tmp &= ~0xffff;
tmp |= 0x3fff;
mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
/* workaround for WDTIMEOUT , set to 550 ms */
mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
/* not to halt for different port op during wideport link change */
mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
/* workaround for Seagate disk not-found OOB sequence, recv
* COMINIT before sending out COMWAKE */
tmp = mvs_cr32(mvi, CMD_PHY_MODE_21);
tmp &= 0x0000ffff;
tmp |= 0x00fa0000;
mvs_cw32(mvi, CMD_PHY_MODE_21, tmp);
tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
tmp &= 0x1fffffff;
tmp |= (2U << 29); /* 8 ms retry */
mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
}
static inline void mvs_int_sata(struct mvs_info *mvi)
{
u32 tmp;
void __iomem *regs = mvi->regs;
tmp = mr32(MVS_INT_STAT_SRS_0);
if (tmp)
mw32(MVS_INT_STAT_SRS_0, tmp);
MVS_CHIP_DISP->clear_active_cmds(mvi);
}
static inline void mvs_int_full(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs;
u32 tmp, stat;
int i;
stat = mr32(MVS_INT_STAT);
mvs_int_rx(mvi, false);
for (i = 0; i < mvi->chip->n_phy; i++) {
tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
if (tmp)
mvs_int_port(mvi, i, tmp);
}
if (stat & CINT_SRS)
mvs_int_sata(mvi);
mw32(MVS_INT_STAT, stat);
}
static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
{
void __iomem *regs = mvi->regs;
mw32(MVS_TX_PROD_IDX, tx);
}
static inline u32 mvs_rx_update(struct mvs_info *mvi)
{
void __iomem *regs = mvi->regs;
return mr32(MVS_RX_CONS_IDX);
}
static inline u32 mvs_get_prd_size(void)
{
return sizeof(struct mvs_prd);
}
static inline u32 mvs_get_prd_count(void)
{
return MAX_SG_ENTRY;
}
static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
{
u16 link_stat, link_spd;
const char *spd[] = {
"UnKnown",
"2.5",
"5.0",
};
if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
return;
pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
if (link_spd >= 3)
link_spd = 0;
dev_printk(KERN_INFO, mvi->dev,
"mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
(link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
spd[link_spd]);
}
static inline u32 mvs_hw_max_link_rate(void)
{
return MAX_LINK_RATE;
}
#endif /* _MV_CHIPS_H_ */

197
drivers/scsi/mvsas/mv_defs.h
View File

@ -1,53 +1,66 @@
/* /*
mv_defs.h - Marvell 88SE6440 SAS/SATA support * Marvell 88SE64xx/88SE94xx const head file
*
Copyright 2007 Red Hat, Inc. * Copyright 2007 Red Hat, Inc.
Copyright 2008 Marvell. <kewei@marvell.com> * Copyright 2008 Marvell. <kewei@marvell.com>
*
This program is free software; you can redistribute it and/or * This file is licensed under GPLv2.
modify it under the terms of the GNU General Public License as *
published by the Free Software Foundation; either version 2, * This program is free software; you can redistribute it and/or
or (at your option) any later version. * modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
This program is distributed in the hope that it will be useful, * License.
but WITHOUT ANY WARRANTY; without even the implied warranty *
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * This program is distributed in the hope that it will be useful,
See the GNU General Public License for more details. * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
You should have received a copy of the GNU General Public * General Public License for more details.
License along with this program; see the file COPYING. If not, *
write to the Free Software Foundation, 675 Mass Ave, Cambridge, * You should have received a copy of the GNU General Public License
MA 02139, USA. * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
*/ * USA
*/
#ifndef _MV_DEFS_H_ #ifndef _MV_DEFS_H_
#define _MV_DEFS_H_ #define _MV_DEFS_H_
enum chip_flavors {
chip_6320,
chip_6440,
chip_6485,
chip_9480,
chip_9180,
};
/* driver compile-time configuration */ /* driver compile-time configuration */
enum driver_configuration { enum driver_configuration {
MVS_SLOTS = 512, /* command slots */
MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */ MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */ MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
/* software requires power-of-2 /* software requires power-of-2
ring size */ ring size */
MVS_SOC_SLOTS = 64,
MVS_SOC_TX_RING_SZ = MVS_SOC_SLOTS * 2,
MVS_SOC_RX_RING_SZ = MVS_SOC_SLOTS * 2,
MVS_SLOTS = 512, /* command slots */
MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */ MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */ MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */ MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
MVS_OAF_SZ = 64, /* Open address frame buffer size */ MVS_OAF_SZ = 64, /* Open address frame buffer size */
MVS_QUEUE_SIZE = 32, /* Support Queue depth */
MVS_RX_FIS_COUNT = 17, /* Optional rx'd FISs (max 17) */ MVS_CAN_QUEUE = MVS_SLOTS - 2, /* SCSI Queue depth */
MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
MVS_QUEUE_SIZE = 30, /* Support Queue depth */
MVS_CAN_QUEUE = MVS_SLOTS - 1, /* SCSI Queue depth */
}; };
/* unchangeable hardware details */ /* unchangeable hardware details */
enum hardware_details { enum hardware_details {
MVS_MAX_PHYS = 8, /* max. possible phys */ MVS_MAX_PHYS = 8, /* max. possible phys */
MVS_MAX_PORTS = 8, /* max. possible ports */ MVS_MAX_PORTS = 8, /* max. possible ports */
MVS_RX_FISL_SZ = 0x400 + (MVS_RX_FIS_COUNT * 0x100), MVS_SOC_PHYS = 4, /* soc phys */
MVS_SOC_PORTS = 4, /* soc phys */
MVS_MAX_DEVICES = 1024, /* max supported device */
}; };
/* peripheral registers (BAR2) */ /* peripheral registers (BAR2) */
@ -133,6 +146,8 @@ enum hw_register_bits {
CINT_PORT = (1U << 8), /* port0 event */ CINT_PORT = (1U << 8), /* port0 event */
CINT_PORT_MASK_OFFSET = 8, CINT_PORT_MASK_OFFSET = 8,
CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET), CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
CINT_PHY_MASK_OFFSET = 4,
CINT_PHY_MASK = (0x0F << CINT_PHY_MASK_OFFSET),
/* TX (delivery) ring bits */ /* TX (delivery) ring bits */
TXQ_CMD_SHIFT = 29, TXQ_CMD_SHIFT = 29,
@ -142,7 +157,11 @@ enum hw_register_bits {
TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */ TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */
TXQ_CMD_SLOT_RESET = 7, /* reset command slot */ TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */ TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
TXQ_MODE_TARGET = 0,
TXQ_MODE_INITIATOR = 1,
TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */ TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
TXQ_PRI_NORMAL = 0,
TXQ_PRI_HIGH = 1,
TXQ_SRS_SHIFT = 20, /* SATA register set */ TXQ_SRS_SHIFT = 20, /* SATA register set */
TXQ_SRS_MASK = 0x7f, TXQ_SRS_MASK = 0x7f,
TXQ_PHY_SHIFT = 12, /* PHY bitmap */ TXQ_PHY_SHIFT = 12, /* PHY bitmap */
@ -175,6 +194,8 @@ enum hw_register_bits {
MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */ MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */ MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
MCH_SSP_MODE_PASSTHRU = 1,
MCH_SSP_MODE_NORMAL = 0,
MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */ MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
MCH_FBURST = (1U << 11), /* first burst (SSP) */ MCH_FBURST = (1U << 11), /* first burst (SSP) */
MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */ MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
@ -199,15 +220,12 @@ enum hw_register_bits {
PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */ PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */ PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
PHY_RST = (1U << 0), /* phy reset */ PHY_RST = (1U << 0), /* phy reset */
PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
(0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
PHY_READY_MASK = (1U << 20), PHY_READY_MASK = (1U << 20),
/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */ /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */ PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
PHYEV_DCDR_ERR = (1U << 23), /* STP Deocder Error */
PHYEV_CRC_ERR = (1U << 22), /* STP CRC Error */
PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */ PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
PHYEV_AN = (1U << 18), /* SATA async notification */ PHYEV_AN = (1U << 18), /* SATA async notification */
PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */ PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
@ -229,9 +247,10 @@ enum hw_register_bits {
/* MVS_PCS */ /* MVS_PCS */
PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */ PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */ PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6480 */ PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6485 */
PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */ PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
PCS_RSP_RX_EN = (1U << 7), /* raw response rx */ PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
PCS_SATA_RETRY_2 = (1U << 6), /* For 9180 */
PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */ PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */ PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */ PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
@ -246,6 +265,8 @@ enum hw_register_bits {
PORT_DEV_SMP_INIT = (1U << 10), PORT_DEV_SMP_INIT = (1U << 10),
PORT_DEV_STP_INIT = (1U << 9), PORT_DEV_STP_INIT = (1U << 9),
PORT_PHY_ID_MASK = (0xFFU << 24), PORT_PHY_ID_MASK = (0xFFU << 24),
PORT_SSP_TRGT_MASK = (0x1U << 19),
PORT_SSP_INIT_MASK = (0x1U << 11),
PORT_DEV_TRGT_MASK = (0x7U << 17), PORT_DEV_TRGT_MASK = (0x7U << 17),
PORT_DEV_INIT_MASK = (0x7U << 9), PORT_DEV_INIT_MASK = (0x7U << 9),
PORT_DEV_TYPE_MASK = (0x7U << 0), PORT_DEV_TYPE_MASK = (0x7U << 0),
@ -283,21 +304,30 @@ enum sas_sata_config_port_regs {
PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */ PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
PHYR_SATA_CTL = 0x18, /* SATA control */ PHYR_SATA_CTL = 0x18, /* SATA control */
PHYR_PHY_STAT = 0x1C, /* PHY status */ PHYR_PHY_STAT = 0x1C, /* PHY status */
PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */ PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */ PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */ PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */ PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */ PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */ PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
PHYR_WIDE_PORT = 0x38, /* wide port participating */ PHYR_WIDE_PORT = 0x38, /* wide port participating */
PHYR_CURRENT0 = 0x80, /* current connection info 0 */ PHYR_CURRENT0 = 0x80, /* current connection info 0 */
PHYR_CURRENT1 = 0x84, /* current connection info 1 */ PHYR_CURRENT1 = 0x84, /* current connection info 1 */
PHYR_CURRENT2 = 0x88, /* current connection info 2 */ PHYR_CURRENT2 = 0x88, /* current connection info 2 */
}; CONFIG_ID_FRAME0 = 0x100, /* Port device ID frame register 0 */
CONFIG_ID_FRAME1 = 0x104, /* Port device ID frame register 1 */
enum mvs_info_flags { CONFIG_ID_FRAME2 = 0x108, /* Port device ID frame register 2 */
MVF_MSI = (1U << 0), /* MSI is enabled */ CONFIG_ID_FRAME3 = 0x10c, /* Port device ID frame register 3 */
MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */ CONFIG_ID_FRAME4 = 0x110, /* Port device ID frame register 4 */
CONFIG_ID_FRAME5 = 0x114, /* Port device ID frame register 5 */
CONFIG_ID_FRAME6 = 0x118, /* Port device ID frame register 6 */
CONFIG_ATT_ID_FRAME0 = 0x11c, /* attached ID frame register 0 */
CONFIG_ATT_ID_FRAME1 = 0x120, /* attached ID frame register 1 */
CONFIG_ATT_ID_FRAME2 = 0x124, /* attached ID frame register 2 */
CONFIG_ATT_ID_FRAME3 = 0x128, /* attached ID frame register 3 */
CONFIG_ATT_ID_FRAME4 = 0x12c, /* attached ID frame register 4 */
CONFIG_ATT_ID_FRAME5 = 0x130, /* attached ID frame register 5 */
CONFIG_ATT_ID_FRAME6 = 0x134, /* attached ID frame register 6 */
}; };
enum sas_cmd_port_registers { enum sas_cmd_port_registers {
@ -305,11 +335,11 @@ enum sas_cmd_port_registers {
CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */ CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */ CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */ CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
CMD_OOB_SPACE = 0x110, /* OOB space control register */ CMD_OOB_SPACE = 0x110, /* OOB space control register */
CMD_OOB_BURST = 0x114, /* OOB burst control register */ CMD_OOB_BURST = 0x114, /* OOB burst control register */
CMD_PHY_TIMER = 0x118, /* PHY timer control register */ CMD_PHY_TIMER = 0x118, /* PHY timer control register */
CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */ CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */ CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */ CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */ CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */ CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
@ -318,9 +348,9 @@ enum sas_cmd_port_registers {
CMD_PL_TIMER = 0x138, /* PL timer register */ CMD_PL_TIMER = 0x138, /* PL timer register */
CMD_WD_TIMER = 0x13c, /* WD timer register */ CMD_WD_TIMER = 0x13c, /* WD timer register */
CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */ CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */ CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */ CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */ CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */ CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */ CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */ CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
@ -353,27 +383,25 @@ enum sas_cmd_port_registers {
CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */ CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
}; };
enum pci_cfg_register_bits { enum mvs_info_flags {
PCTL_PWR_ON = (0xFU << 24), MVF_MSI = (1U << 0), /* MSI is enabled */
PCTL_OFF = (0xFU << 12), MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
PRD_REQ_SIZE = (0x4000), MVF_FLAG_SOC = (1U << 2), /* SoC integrated controllers */
PRD_REQ_MASK = (0x00007000),
}; };
enum nvram_layout_offsets { enum mvs_event_flags {
NVR_SIG = 0x00, /* 0xAA, 0x55 */ PHY_PLUG_EVENT = (3U),
NVR_SAS_ADDR = 0x02, /* 8-byte SAS address */ PHY_PLUG_IN = (1U << 0), /* phy plug in */
PHY_PLUG_OUT = (1U << 1), /* phy plug out */
}; };
enum chip_flavors { enum mvs_port_type {
chip_6320, PORT_TGT_MASK = (1U << 5),
chip_6440, PORT_INIT_PORT = (1U << 4),
chip_6480, PORT_TGT_PORT = (1U << 3),
}; PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
PORT_TYPE_SAS = (1U << 1),
enum port_type { PORT_TYPE_SATA = (1U << 0),
PORT_TYPE_SAS = (1L << 1),
PORT_TYPE_SATA = (1L << 0),
}; };
/* Command Table Format */ /* Command Table Format */
@ -438,4 +466,37 @@ enum error_info_rec_2 {
USR_BLK_NM = (1U << 0), /* User Block Number */ USR_BLK_NM = (1U << 0), /* User Block Number */
}; };
enum pci_cfg_register_bits {
PCTL_PWR_OFF = (0xFU << 24),
PCTL_COM_ON = (0xFU << 20),
PCTL_LINK_RST = (0xFU << 16),
PCTL_LINK_OFFS = (16),
PCTL_PHY_DSBL = (0xFU << 12),
PCTL_PHY_DSBL_OFFS = (12),
PRD_REQ_SIZE = (0x4000),
PRD_REQ_MASK = (0x00007000),
PLS_NEG_LINK_WD = (0x3FU << 4),
PLS_NEG_LINK_WD_OFFS = 4,
PLS_LINK_SPD = (0x0FU << 0),
PLS_LINK_SPD_OFFS = 0,
};
enum open_frame_protocol {
PROTOCOL_SMP = 0x0,
PROTOCOL_SSP = 0x1,
PROTOCOL_STP = 0x2,
};
/* define for response frame datapres field */
enum datapres_field {
NO_DATA = 0,
RESPONSE_DATA = 1,
SENSE_DATA = 2,
};
/* define task management IU */
struct mvs_tmf_task{
u8 tmf;
u16 tag_of_task_to_be_managed;
};
#endif #endif

629
drivers/scsi/mvsas/mv_init.c
View File

@ -1,38 +1,41 @@
/* /*
mv_init.c - Marvell 88SE6440 SAS/SATA init support * Marvell 88SE64xx/88SE94xx pci init
*
* Copyright 2007 Red Hat, Inc.
* Copyright 2008 Marvell. <kewei@marvell.com>
*
* This file is licensed under GPLv2.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
* USA
*/
Copyright 2007 Red Hat, Inc.
Copyright 2008 Marvell. <kewei@marvell.com>
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2,
or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public
License along with this program; see the file COPYING. If not,
write to the Free Software Foundation, 675 Mass Ave, Cambridge,
MA 02139, USA.
*/
#include "mv_sas.h" #include "mv_sas.h"
#include "mv_64xx.h"
#include "mv_chips.h"
static struct scsi_transport_template *mvs_stt; static struct scsi_transport_template *mvs_stt;
static const struct mvs_chip_info mvs_chips[] = { static const struct mvs_chip_info mvs_chips[] = {
[chip_6320] = { 2, 16, 9 }, [chip_6320] = { 1, 2, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
[chip_6440] = { 4, 16, 9 }, [chip_6440] = { 1, 4, 0x400, 17, 16, 9, &mvs_64xx_dispatch, },
[chip_6480] = { 8, 32, 10 }, [chip_6485] = { 1, 8, 0x800, 33, 32, 10, &mvs_64xx_dispatch, },
[chip_9180] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
[chip_9480] = { 2, 4, 0x800, 17, 64, 9, &mvs_94xx_dispatch, },
}; };
#define SOC_SAS_NUM 2
static struct scsi_host_template mvs_sht = { static struct scsi_host_template mvs_sht = {
.module = THIS_MODULE, .module = THIS_MODULE,
.name = DRV_NAME, .name = DRV_NAME,
@ -53,17 +56,29 @@ static struct scsi_host_template mvs_sht = {
.use_clustering = ENABLE_CLUSTERING, .use_clustering = ENABLE_CLUSTERING,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_bus_reset_handler = sas_eh_bus_reset_handler, .eh_bus_reset_handler = sas_eh_bus_reset_handler,
.slave_alloc = sas_slave_alloc, .slave_alloc = mvs_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
}; };
static struct sas_domain_function_template mvs_transport_ops = { static struct sas_domain_function_template mvs_transport_ops = {
.lldd_execute_task = mvs_task_exec, .lldd_dev_found = mvs_dev_found,
.lldd_dev_gone = mvs_dev_gone,
.lldd_execute_task = mvs_queue_command,
.lldd_control_phy = mvs_phy_control, .lldd_control_phy = mvs_phy_control,
.lldd_abort_task = mvs_task_abort,
.lldd_port_formed = mvs_port_formed, .lldd_abort_task = mvs_abort_task,
.lldd_abort_task_set = mvs_abort_task_set,
.lldd_clear_aca = mvs_clear_aca,
.lldd_clear_task_set = mvs_clear_task_set,
.lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,
.lldd_lu_reset = mvs_lu_reset,
.lldd_query_task = mvs_query_task,
.lldd_port_formed = mvs_port_formed,
.lldd_port_deformed = mvs_port_deformed,
}; };
static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id) static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
@ -71,6 +86,8 @@ static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
struct mvs_phy *phy = &mvi->phy[phy_id]; struct mvs_phy *phy = &mvi->phy[phy_id];
struct asd_sas_phy *sas_phy = &phy->sas_phy; struct asd_sas_phy *sas_phy = &phy->sas_phy;
phy->mvi = mvi;
init_timer(&phy->timer);
sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
sas_phy->class = SAS; sas_phy->class = SAS;
sas_phy->iproto = SAS_PROTOCOL_ALL; sas_phy->iproto = SAS_PROTOCOL_ALL;
@ -83,248 +100,283 @@ static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
sas_phy->id = phy_id; sas_phy->id = phy_id;
sas_phy->sas_addr = &mvi->sas_addr[0]; sas_phy->sas_addr = &mvi->sas_addr[0];
sas_phy->frame_rcvd = &phy->frame_rcvd[0]; sas_phy->frame_rcvd = &phy->frame_rcvd[0];
sas_phy->ha = &mvi->sas; sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;
sas_phy->lldd_phy = phy; sas_phy->lldd_phy = phy;
} }
static void mvs_free(struct mvs_info *mvi) static void mvs_free(struct mvs_info *mvi)
{ {
int i; int i;
struct mvs_wq *mwq;
int slot_nr;
if (!mvi) if (!mvi)
return; return;
for (i = 0; i < MVS_SLOTS; i++) { if (mvi->flags & MVF_FLAG_SOC)
struct mvs_slot_info *slot = &mvi->slot_info[i]; slot_nr = MVS_SOC_SLOTS;
else
slot_nr = MVS_SLOTS;
for (i = 0; i < mvi->tags_num; i++) {
struct mvs_slot_info *slot = &mvi->slot_info[i];
if (slot->buf) if (slot->buf)
dma_free_coherent(&mvi->pdev->dev, MVS_SLOT_BUF_SZ, dma_free_coherent(mvi->dev, MVS_SLOT_BUF_SZ,
slot->buf, slot->buf_dma); slot->buf, slot->buf_dma);
} }
if (mvi->tx) if (mvi->tx)
dma_free_coherent(&mvi->pdev->dev, dma_free_coherent(mvi->dev,
sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
mvi->tx, mvi->tx_dma); mvi->tx, mvi->tx_dma);
if (mvi->rx_fis) if (mvi->rx_fis)
dma_free_coherent(&mvi->pdev->dev, MVS_RX_FISL_SZ, dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,
mvi->rx_fis, mvi->rx_fis_dma); mvi->rx_fis, mvi->rx_fis_dma);
if (mvi->rx) if (mvi->rx)
dma_free_coherent(&mvi->pdev->dev, dma_free_coherent(mvi->dev,
sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
mvi->rx, mvi->rx_dma); mvi->rx, mvi->rx_dma);
if (mvi->slot) if (mvi->slot)
dma_free_coherent(&mvi->pdev->dev, dma_free_coherent(mvi->dev,
sizeof(*mvi->slot) * MVS_SLOTS, sizeof(*mvi->slot) * slot_nr,
mvi->slot, mvi->slot_dma); mvi->slot, mvi->slot_dma);
#ifdef MVS_ENABLE_PERI #ifndef DISABLE_HOTPLUG_DMA_FIX
if (mvi->peri_regs) if (mvi->bulk_buffer)
iounmap(mvi->peri_regs); dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,
mvi->bulk_buffer, mvi->bulk_buffer_dma);
#endif #endif
if (mvi->regs)
iounmap(mvi->regs); MVS_CHIP_DISP->chip_iounmap(mvi);
if (mvi->shost) if (mvi->shost)
scsi_host_put(mvi->shost); scsi_host_put(mvi->shost);
kfree(mvi->sas.sas_port); list_for_each_entry(mwq, &mvi->wq_list, entry)
kfree(mvi->sas.sas_phy); cancel_delayed_work(&mwq->work_q);
kfree(mvi); kfree(mvi);
} }
#ifdef MVS_USE_TASKLET #ifdef MVS_USE_TASKLET
static void mvs_tasklet(unsigned long data) struct tasklet_struct mv_tasklet;
static void mvs_tasklet(unsigned long opaque)
{ {
struct mvs_info *mvi = (struct mvs_info *) data;
unsigned long flags; unsigned long flags;
u32 stat;
u16 core_nr, i = 0;
spin_lock_irqsave(&mvi->lock, flags); struct mvs_info *mvi;
struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
if (unlikely(!mvi))
BUG_ON(1);
for (i = 0; i < core_nr; i++) {
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
stat = MVS_CHIP_DISP->isr_status(mvi, mvi->irq);
if (stat)
MVS_CHIP_DISP->isr(mvi, mvi->irq, stat);
}
#ifdef MVS_DISABLE_MSI
mvs_int_full(mvi);
#else
mvs_int_rx(mvi, true);
#endif
spin_unlock_irqrestore(&mvi->lock, flags);
} }
#endif #endif
static irqreturn_t mvs_interrupt(int irq, void *opaque) static irqreturn_t mvs_interrupt(int irq, void *opaque)
{ {
struct mvs_info *mvi = opaque; u32 core_nr, i = 0;
void __iomem *regs = mvi->regs;
u32 stat; u32 stat;
struct mvs_info *mvi;
struct sas_ha_struct *sha = opaque;
stat = mr32(GBL_INT_STAT); core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
if (stat == 0 || stat == 0xffffffff) if (unlikely(!mvi))
return IRQ_NONE; return IRQ_NONE;
/* clear CMD_CMPLT ASAP */ stat = MVS_CHIP_DISP->isr_status(mvi, irq);
mw32_f(INT_STAT, CINT_DONE); if (!stat)
return IRQ_NONE;
#ifndef MVS_USE_TASKLET #ifdef MVS_USE_TASKLET
spin_lock(&mvi->lock); tasklet_schedule(&mv_tasklet);
mvs_int_full(mvi);
spin_unlock(&mvi->lock);
#else #else
tasklet_schedule(&mvi->tasklet); for (i = 0; i < core_nr; i++) {
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
MVS_CHIP_DISP->isr(mvi, irq, stat);
}
#endif #endif
return IRQ_HANDLED; return IRQ_HANDLED;
} }
static struct mvs_info *__devinit mvs_alloc(struct pci_dev *pdev, static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)
const struct pci_device_id *ent)
{ {
struct mvs_info *mvi; int i, slot_nr;
unsigned long res_start, res_len, res_flag;
struct asd_sas_phy **arr_phy;
struct asd_sas_port **arr_port;
const struct mvs_chip_info *chip = &mvs_chips[ent->driver_data];
int i;
/* if (mvi->flags & MVF_FLAG_SOC)
* alloc and init our per-HBA mvs_info struct slot_nr = MVS_SOC_SLOTS;
*/ else
slot_nr = MVS_SLOTS;
mvi = kzalloc(sizeof(*mvi), GFP_KERNEL);
if (!mvi)
return NULL;
spin_lock_init(&mvi->lock); spin_lock_init(&mvi->lock);
#ifdef MVS_USE_TASKLET for (i = 0; i < mvi->chip->n_phy; i++) {
tasklet_init(&mvi->tasklet, mvs_tasklet, (unsigned long)mvi);
#endif
mvi->pdev = pdev;
mvi->chip = chip;
if (pdev->device == 0x6440 && pdev->revision == 0)
mvi->flags |= MVF_PHY_PWR_FIX;
/*
* alloc and init SCSI, SAS glue
*/
mvi->shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
if (!mvi->shost)
goto err_out;
arr_phy = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
arr_port = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
if (!arr_phy || !arr_port)
goto err_out;
for (i = 0; i < MVS_MAX_PHYS; i++) {
mvs_phy_init(mvi, i); mvs_phy_init(mvi, i);
arr_phy[i] = &mvi->phy[i].sas_phy;
arr_port[i] = &mvi->port[i].sas_port;
mvi->port[i].taskfileset = MVS_ID_NOT_MAPPED;
mvi->port[i].wide_port_phymap = 0; mvi->port[i].wide_port_phymap = 0;
mvi->port[i].port_attached = 0; mvi->port[i].port_attached = 0;
INIT_LIST_HEAD(&mvi->port[i].list); INIT_LIST_HEAD(&mvi->port[i].list);
} }
for (i = 0; i < MVS_MAX_DEVICES; i++) {
SHOST_TO_SAS_HA(mvi->shost) = &mvi->sas; mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;
mvi->shost->transportt = mvs_stt; mvi->devices[i].dev_type = NO_DEVICE;
mvi->shost->max_id = 21; mvi->devices[i].device_id = i;
mvi->shost->max_lun = ~0; mvi->devices[i].dev_status = MVS_DEV_NORMAL;
mvi->shost->max_channel = 0; }
mvi->shost->max_cmd_len = 16;
mvi->sas.sas_ha_name = DRV_NAME;
mvi->sas.dev = &pdev->dev;
mvi->sas.lldd_module = THIS_MODULE;
mvi->sas.sas_addr = &mvi->sas_addr[0];
mvi->sas.sas_phy = arr_phy;
mvi->sas.sas_port = arr_port;
mvi->sas.num_phys = chip->n_phy;
mvi->sas.lldd_max_execute_num = 1;
mvi->sas.lldd_queue_size = MVS_QUEUE_SIZE;
mvi->shost->can_queue = MVS_CAN_QUEUE;
mvi->shost->cmd_per_lun = MVS_SLOTS / mvi->sas.num_phys;
mvi->sas.lldd_ha = mvi;
mvi->sas.core.shost = mvi->shost;
mvs_tag_init(mvi);
/*
* ioremap main and peripheral registers
*/
#ifdef MVS_ENABLE_PERI
res_start = pci_resource_start(pdev, 2);
res_len = pci_resource_len(pdev, 2);
if (!res_start || !res_len)
goto err_out;
mvi->peri_regs = ioremap_nocache(res_start, res_len);
if (!mvi->peri_regs)
goto err_out;
#endif
res_start = pci_resource_start(pdev, 4);
res_len = pci_resource_len(pdev, 4);
if (!res_start || !res_len)
goto err_out;
res_flag = pci_resource_flags(pdev, 4);
if (res_flag & IORESOURCE_CACHEABLE)
mvi->regs = ioremap(res_start, res_len);
else
mvi->regs = ioremap_nocache(res_start, res_len);
if (!mvi->regs)
goto err_out;
/* /*
* alloc and init our DMA areas * alloc and init our DMA areas
*/ */
mvi->tx = dma_alloc_coherent(mvi->dev,
mvi->tx = dma_alloc_coherent(&pdev->dev,
sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
&mvi->tx_dma, GFP_KERNEL); &mvi->tx_dma, GFP_KERNEL);
if (!mvi->tx) if (!mvi->tx)
goto err_out; goto err_out;
memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,
mvi->rx_fis = dma_alloc_coherent(&pdev->dev, MVS_RX_FISL_SZ,
&mvi->rx_fis_dma, GFP_KERNEL); &mvi->rx_fis_dma, GFP_KERNEL);
if (!mvi->rx_fis) if (!mvi->rx_fis)
goto err_out; goto err_out;
memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
mvi->rx = dma_alloc_coherent(&pdev->dev, mvi->rx = dma_alloc_coherent(mvi->dev,
sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),
&mvi->rx_dma, GFP_KERNEL); &mvi->rx_dma, GFP_KERNEL);
if (!mvi->rx) if (!mvi->rx)
goto err_out; goto err_out;
memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1));
mvi->rx[0] = cpu_to_le32(0xfff); mvi->rx[0] = cpu_to_le32(0xfff);
mvi->rx_cons = 0xfff; mvi->rx_cons = 0xfff;
mvi->slot = dma_alloc_coherent(&pdev->dev, mvi->slot = dma_alloc_coherent(mvi->dev,
sizeof(*mvi->slot) * MVS_SLOTS, sizeof(*mvi->slot) * slot_nr,
&mvi->slot_dma, GFP_KERNEL); &mvi->slot_dma, GFP_KERNEL);
if (!mvi->slot) if (!mvi->slot)
goto err_out; goto err_out;
memset(mvi->slot, 0, sizeof(*mvi->slot) * MVS_SLOTS); memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr);
for (i = 0; i < MVS_SLOTS; i++) { #ifndef DISABLE_HOTPLUG_DMA_FIX
mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,
TRASH_BUCKET_SIZE,
&mvi->bulk_buffer_dma, GFP_KERNEL);
if (!mvi->bulk_buffer)
goto err_out;
#endif
for (i = 0; i < slot_nr; i++) {
struct mvs_slot_info *slot = &mvi->slot_info[i]; struct mvs_slot_info *slot = &mvi->slot_info[i];
slot->buf = dma_alloc_coherent(&pdev->dev, MVS_SLOT_BUF_SZ, slot->buf = dma_alloc_coherent(mvi->dev, MVS_SLOT_BUF_SZ,
&slot->buf_dma, GFP_KERNEL); &slot->buf_dma, GFP_KERNEL);
if (!slot->buf) if (!slot->buf) {
printk(KERN_DEBUG"failed to allocate slot->buf.\n");
goto err_out; goto err_out;
}
memset(slot->buf, 0, MVS_SLOT_BUF_SZ); memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
++mvi->tags_num;
}
/* Initialize tags */
mvs_tag_init(mvi);
return 0;
err_out:
return 1;
}
int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)
{
unsigned long res_start, res_len, res_flag, res_flag_ex = 0;
struct pci_dev *pdev = mvi->pdev;
if (bar_ex != -1) {
/*
* ioremap main and peripheral registers
*/
res_start = pci_resource_start(pdev, bar_ex);
res_len = pci_resource_len(pdev, bar_ex);
if (!res_start || !res_len)
goto err_out;
res_flag_ex = pci_resource_flags(pdev, bar_ex);
if (res_flag_ex & IORESOURCE_MEM) {
if (res_flag_ex & IORESOURCE_CACHEABLE)
mvi->regs_ex = ioremap(res_start, res_len);
else
mvi->regs_ex = ioremap_nocache(res_start,
res_len);
} else
mvi->regs_ex = (void *)res_start;
if (!mvi->regs_ex)
goto err_out;
} }
/* finally, read NVRAM to get our SAS address */ res_start = pci_resource_start(pdev, bar);
if (mvs_nvram_read(mvi, NVR_SAS_ADDR, &mvi->sas_addr, 8)) res_len = pci_resource_len(pdev, bar);
if (!res_start || !res_len)
goto err_out; goto err_out;
return mvi;
res_flag = pci_resource_flags(pdev, bar);
if (res_flag & IORESOURCE_CACHEABLE)
mvi->regs = ioremap(res_start, res_len);
else
mvi->regs = ioremap_nocache(res_start, res_len);
if (!mvi->regs) {
if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))
iounmap(mvi->regs_ex);
mvi->regs_ex = NULL;
goto err_out;
}
return 0;
err_out:
return -1;
}
void mvs_iounmap(void __iomem *regs)
{
iounmap(regs);
}
static struct mvs_info *__devinit mvs_pci_alloc(struct pci_dev *pdev,
const struct pci_device_id *ent,
struct Scsi_Host *shost, unsigned int id)
{
struct mvs_info *mvi;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
mvi = kzalloc(sizeof(*mvi) + MVS_SLOTS * sizeof(struct mvs_slot_info),
GFP_KERNEL);
if (!mvi)
return NULL;
mvi->pdev = pdev;
mvi->dev = &pdev->dev;
mvi->chip_id = ent->driver_data;
mvi->chip = &mvs_chips[mvi->chip_id];
INIT_LIST_HEAD(&mvi->wq_list);
mvi->irq = pdev->irq;
((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;
((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;
mvi->id = id;
mvi->sas = sha;
mvi->shost = shost;
#ifdef MVS_USE_TASKLET
tasklet_init(&mv_tasklet, mvs_tasklet, (unsigned long)sha);
#endif
if (MVS_CHIP_DISP->chip_ioremap(mvi))
goto err_out;
if (!mvs_alloc(mvi, shost))
return mvi;
err_out: err_out:
mvs_free(mvi); mvs_free(mvi);
return NULL; return NULL;
@ -363,16 +415,111 @@ static int pci_go_64(struct pci_dev *pdev)
return rc; return rc;
} }
static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost,
const struct mvs_chip_info *chip_info)
{
int phy_nr, port_nr; unsigned short core_nr;
struct asd_sas_phy **arr_phy;
struct asd_sas_port **arr_port;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
core_nr = chip_info->n_host;
phy_nr = core_nr * chip_info->n_phy;
port_nr = phy_nr;
memset(sha, 0x00, sizeof(struct sas_ha_struct));
arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
if (!arr_phy || !arr_port)
goto exit_free;
sha->sas_phy = arr_phy;
sha->sas_port = arr_port;
sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);
if (!sha->lldd_ha)
goto exit_free;
((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;
shost->transportt = mvs_stt;
shost->max_id = 128;
shost->max_lun = ~0;
shost->max_channel = 1;
shost->max_cmd_len = 16;
return 0;
exit_free:
kfree(arr_phy);
kfree(arr_port);
return -1;
}
static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost,
const struct mvs_chip_info *chip_info)
{
int can_queue, i = 0, j = 0;
struct mvs_info *mvi = NULL;
struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
for (j = 0; j < nr_core; j++) {
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
for (i = 0; i < chip_info->n_phy; i++) {
sha->sas_phy[j * chip_info->n_phy + i] =
&mvi->phy[i].sas_phy;
sha->sas_port[j * chip_info->n_phy + i] =
&mvi->port[i].sas_port;
}
}
sha->sas_ha_name = DRV_NAME;
sha->dev = mvi->dev;
sha->lldd_module = THIS_MODULE;
sha->sas_addr = &mvi->sas_addr[0];
sha->num_phys = nr_core * chip_info->n_phy;
sha->lldd_max_execute_num = 1;
if (mvi->flags & MVF_FLAG_SOC)
can_queue = MVS_SOC_CAN_QUEUE;
else
can_queue = MVS_CAN_QUEUE;
sha->lldd_queue_size = can_queue;
shost->can_queue = can_queue;
mvi->shost->cmd_per_lun = MVS_SLOTS/sha->num_phys;
sha->core.shost = mvi->shost;
}
static void mvs_init_sas_add(struct mvs_info *mvi)
{
u8 i;
for (i = 0; i < mvi->chip->n_phy; i++) {
mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;
mvi->phy[i].dev_sas_addr =
cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));
}
memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);
}
static int __devinit mvs_pci_init(struct pci_dev *pdev, static int __devinit mvs_pci_init(struct pci_dev *pdev,
const struct pci_device_id *ent) const struct pci_device_id *ent)
{ {
int rc; unsigned int rc, nhost = 0;
struct mvs_info *mvi; struct mvs_info *mvi;
irq_handler_t irq_handler = mvs_interrupt; irq_handler_t irq_handler = mvs_interrupt;
struct Scsi_Host *shost = NULL;
const struct mvs_chip_info *chip;
dev_printk(KERN_INFO, &pdev->dev,
"mvsas: driver version %s\n", DRV_VERSION);
rc = pci_enable_device(pdev); rc = pci_enable_device(pdev);
if (rc) if (rc)
return rc; goto err_out_enable;
pci_set_master(pdev); pci_set_master(pdev);
@ -384,84 +531,110 @@ static int __devinit mvs_pci_init(struct pci_dev *pdev,
if (rc) if (rc)
goto err_out_regions; goto err_out_regions;
mvi = mvs_alloc(pdev, ent); shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
if (!mvi) { if (!shost) {
rc = -ENOMEM; rc = -ENOMEM;
goto err_out_regions; goto err_out_regions;
} }
rc = mvs_hw_init(mvi); chip = &mvs_chips[ent->driver_data];
if (rc) SHOST_TO_SAS_HA(shost) =
goto err_out_mvi; kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);
if (!SHOST_TO_SAS_HA(shost)) {
#ifndef MVS_DISABLE_MSI kfree(shost);
if (!pci_enable_msi(pdev)) { rc = -ENOMEM;
u32 tmp; goto err_out_regions;
void __iomem *regs = mvi->regs;
mvi->flags |= MVF_MSI;
irq_handler = mvs_msi_interrupt;
tmp = mr32(PCS);
mw32(PCS, tmp | PCS_SELF_CLEAR);
} }
#endif
rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME, mvi); rc = mvs_prep_sas_ha_init(shost, chip);
if (rc) if (rc) {
goto err_out_msi; kfree(shost);
rc = -ENOMEM;
goto err_out_regions;
}
rc = scsi_add_host(mvi->shost, &pdev->dev); pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
if (rc)
goto err_out_irq;
rc = sas_register_ha(&mvi->sas); do {
mvi = mvs_pci_alloc(pdev, ent, shost, nhost);
if (!mvi) {
rc = -ENOMEM;
goto err_out_regions;
}
mvs_init_sas_add(mvi);
mvi->instance = nhost;
rc = MVS_CHIP_DISP->chip_init(mvi);
if (rc) {
mvs_free(mvi);
goto err_out_regions;
}
nhost++;
} while (nhost < chip->n_host);
mvs_post_sas_ha_init(shost, chip);
rc = scsi_add_host(shost, &pdev->dev);
if (rc) if (rc)
goto err_out_shost; goto err_out_shost;
pci_set_drvdata(pdev, mvi); rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
if (rc)
goto err_out_shost;
rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,
DRV_NAME, SHOST_TO_SAS_HA(shost));
if (rc)
goto err_not_sas;
mvs_print_info(mvi); MVS_CHIP_DISP->interrupt_enable(mvi);
mvs_hba_interrupt_enable(mvi);
scsi_scan_host(mvi->shost); scsi_scan_host(mvi->shost);
return 0; return 0;
err_not_sas:
sas_unregister_ha(SHOST_TO_SAS_HA(shost));
err_out_shost: err_out_shost:
scsi_remove_host(mvi->shost); scsi_remove_host(mvi->shost);
err_out_irq:
free_irq(pdev->irq, mvi);
err_out_msi:
if (mvi->flags |= MVF_MSI)
pci_disable_msi(pdev);
err_out_mvi:
mvs_free(mvi);
err_out_regions: err_out_regions:
pci_release_regions(pdev); pci_release_regions(pdev);
err_out_disable: err_out_disable:
pci_disable_device(pdev); pci_disable_device(pdev);
err_out_enable:
return rc; return rc;
} }
static void __devexit mvs_pci_remove(struct pci_dev *pdev) static void __devexit mvs_pci_remove(struct pci_dev *pdev)
{ {
struct mvs_info *mvi = pci_get_drvdata(pdev); unsigned short core_nr, i = 0;
struct sas_ha_struct *sha = pci_get_drvdata(pdev);
struct mvs_info *mvi = NULL;
core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];
#ifdef MVS_USE_TASKLET
tasklet_kill(&mv_tasklet);
#endif
pci_set_drvdata(pdev, NULL); pci_set_drvdata(pdev, NULL);
sas_unregister_ha(sha);
sas_remove_host(mvi->shost);
scsi_remove_host(mvi->shost);
if (mvi) { MVS_CHIP_DISP->interrupt_disable(mvi);
sas_unregister_ha(&mvi->sas); free_irq(mvi->irq, sha);
mvs_hba_interrupt_disable(mvi); for (i = 0; i < core_nr; i++) {
sas_remove_host(mvi->shost); mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];
scsi_remove_host(mvi->shost);
free_irq(pdev->irq, mvi);
if (mvi->flags & MVF_MSI)
pci_disable_msi(pdev);
mvs_free(mvi); mvs_free(mvi);
pci_release_regions(pdev);
} }
kfree(sha->sas_phy);
kfree(sha->sas_port);
kfree(sha);
pci_release_regions(pdev);
pci_disable_device(pdev); pci_disable_device(pdev);
return;
} }
static struct pci_device_id __devinitdata mvs_pci_table[] = { static struct pci_device_id __devinitdata mvs_pci_table[] = {
@ -474,10 +647,12 @@ static struct pci_device_id __devinitdata mvs_pci_table[] = {
.subdevice = 0x6480, .subdevice = 0x6480,
.class = 0, .class = 0,
.class_mask = 0, .class_mask = 0,
.driver_data = chip_6480, .driver_data = chip_6485,
}, },
{ PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
{ PCI_VDEVICE(MARVELL, 0x6480), chip_6480 }, { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },
{ PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },
{ PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },
{ } /* terminate list */ { } /* terminate list */
}; };
@ -489,15 +664,17 @@ static struct pci_driver mvs_pci_driver = {
.remove = __devexit_p(mvs_pci_remove), .remove = __devexit_p(mvs_pci_remove),
}; };
/* task handler */
struct task_struct *mvs_th;
static int __init mvs_init(void) static int __init mvs_init(void)
{ {
int rc; int rc;
mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
if (!mvs_stt) if (!mvs_stt)
return -ENOMEM; return -ENOMEM;
rc = pci_register_driver(&mvs_pci_driver); rc = pci_register_driver(&mvs_pci_driver);
if (rc) if (rc)
goto err_out; goto err_out;
@ -521,4 +698,6 @@ MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
MODULE_VERSION(DRV_VERSION); MODULE_VERSION(DRV_VERSION);
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");
#ifdef CONFIG_PCI
MODULE_DEVICE_TABLE(pci, mvs_pci_table); MODULE_DEVICE_TABLE(pci, mvs_pci_table);
#endif

2133
drivers/scsi/mvsas/mv_sas.c
View File

File diff suppressed because it is too large Load Diff

331
drivers/scsi/mvsas/mv_sas.h
View File

@ -1,25 +1,26 @@
/* /*
mv_sas.h - Marvell 88SE6440 SAS/SATA support * Marvell 88SE64xx/88SE94xx main function head file
*
Copyright 2007 Red Hat, Inc. * Copyright 2007 Red Hat, Inc.
Copyright 2008 Marvell. <kewei@marvell.com> * Copyright 2008 Marvell. <kewei@marvell.com>
*
This program is free software; you can redistribute it and/or * This file is licensed under GPLv2.
modify it under the terms of the GNU General Public License as *
published by the Free Software Foundation; either version 2, * This program is free software; you can redistribute it and/or
or (at your option) any later version. * modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the
This program is distributed in the hope that it will be useful, * License.
but WITHOUT ANY WARRANTY; without even the implied warranty *
of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. * This program is distributed in the hope that it will be useful,
See the GNU General Public License for more details. * but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
You should have received a copy of the GNU General Public * General Public License for more details.
License along with this program; see the file COPYING. If not, *
write to the Free Software Foundation, 675 Mass Ave, Cambridge, * You should have received a copy of the GNU General Public License
MA 02139, USA. * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
*/ * USA
*/
#ifndef _MV_SAS_H_ #ifndef _MV_SAS_H_
#define _MV_SAS_H_ #define _MV_SAS_H_
@ -42,26 +43,145 @@
#include <linux/version.h> #include <linux/version.h>
#include "mv_defs.h" #include "mv_defs.h"
#define DRV_NAME "mvsas" #define DRV_NAME "mvsas"
#define DRV_VERSION "0.5.2" #define DRV_VERSION "0.8.2"
#define _MV_DUMP 0 #define _MV_DUMP 0
#define MVS_DISABLE_NVRAM
#define MVS_DISABLE_MSI
#define MVS_ID_NOT_MAPPED 0x7f #define MVS_ID_NOT_MAPPED 0x7f
#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width) /* #define DISABLE_HOTPLUG_DMA_FIX */
#define MAX_EXP_RUNNING_REQ 2
#define WIDE_PORT_MAX_PHY 4
#define MV_DISABLE_NCQ 0
#define mv_printk(fmt, arg ...) \
printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
#ifdef MV_DEBUG
#define mv_dprintk(format, arg...) \
printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
#else
#define mv_dprintk(format, arg...)
#endif
#define MV_MAX_U32 0xffffffff
#define for_each_phy(__lseq_mask, __mc, __lseq, __rest) \ extern struct mvs_tgt_initiator mvs_tgt;
for ((__mc) = (__lseq_mask), (__lseq) = 0; \ extern struct mvs_info *tgt_mvi;
(__mc) != 0 && __rest; \ extern const struct mvs_dispatch mvs_64xx_dispatch;
extern const struct mvs_dispatch mvs_94xx_dispatch;
#define DEV_IS_EXPANDER(type) \
((type == EDGE_DEV) || (type == FANOUT_DEV))
#define bit(n) ((u32)1 << n)
#define for_each_phy(__lseq_mask, __mc, __lseq) \
for ((__mc) = (__lseq_mask), (__lseq) = 0; \
(__mc) != 0 ; \
(++__lseq), (__mc) >>= 1) (++__lseq), (__mc) >>= 1)
struct mvs_chip_info { #define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
u32 n_phy; #define UNASSOC_D2H_FIS(id) \
u32 srs_sz; ((void *) mvi->rx_fis + 0x100 * id)
u32 slot_width; #define SATA_RECEIVED_FIS_LIST(reg_set) \
((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
#define SATA_RECEIVED_SDB_FIS(reg_set) \
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
#define SATA_RECEIVED_D2H_FIS(reg_set) \
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
#define SATA_RECEIVED_PIO_FIS(reg_set) \
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
#define SATA_RECEIVED_DMA_FIS(reg_set) \
(SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
enum dev_status {
MVS_DEV_NORMAL = 0x0,
MVS_DEV_EH = 0x1,
}; };
struct mvs_info;
struct mvs_dispatch {
char *name;
int (*chip_init)(struct mvs_info *mvi);
int (*spi_init)(struct mvs_info *mvi);
int (*chip_ioremap)(struct mvs_info *mvi);
void (*chip_iounmap)(struct mvs_info *mvi);
irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
u32 (*isr_status)(struct mvs_info *mvi, int irq);
void (*interrupt_enable)(struct mvs_info *mvi);
void (*interrupt_disable)(struct mvs_info *mvi);
u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
void (*get_sas_addr)(void *buf, u32 buflen);
void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
u32 tfs);
void (*start_delivery)(struct mvs_info *mvi, u32 tx);
u32 (*rx_update)(struct mvs_info *mvi);
void (*int_full)(struct mvs_info *mvi);
u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
u32 (*prd_size)(void);
u32 (*prd_count)(void);
void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
void (*detect_porttype)(struct mvs_info *mvi, int i);
int (*oob_done)(struct mvs_info *mvi, int i);
void (*fix_phy_info)(struct mvs_info *mvi, int i,
struct sas_identify_frame *id);
void (*phy_work_around)(struct mvs_info *mvi, int i);
void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
struct sas_phy_linkrates *rates);
u32 (*phy_max_link_rate)(void);
void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
void (*clear_active_cmds)(struct mvs_info *mvi);
u32 (*spi_read_data)(struct mvs_info *mvi);
void (*spi_write_data)(struct mvs_info *mvi, u32 data);
int (*spi_buildcmd)(struct mvs_info *mvi,
u32 *dwCmd,
u8 cmd,
u8 read,
u8 length,
u32 addr
);
int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
#ifndef DISABLE_HOTPLUG_DMA_FIX
void (*dma_fix)(dma_addr_t buf_dma, int buf_len, int from, void *prd);
#endif
};
struct mvs_chip_info {
u32 n_host;
u32 n_phy;
u32 fis_offs;
u32 fis_count;
u32 srs_sz;
u32 slot_width;
const struct mvs_dispatch *dispatch;
};
#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
#define MVS_RX_FISL_SZ \
(mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
#define MVS_CHIP_DISP (mvi->chip->dispatch)
struct mvs_err_info { struct mvs_err_info {
__le32 flags; __le32 flags;
__le32 flags2; __le32 flags2;
@ -72,7 +192,7 @@ struct mvs_cmd_hdr {
__le32 lens; /* cmd, max resp frame len */ __le32 lens; /* cmd, max resp frame len */
__le32 tags; /* targ port xfer tag; tag */ __le32 tags; /* targ port xfer tag; tag */
__le32 data_len; /* data xfer len */ __le32 data_len; /* data xfer len */
__le64 cmd_tbl; /* command table address */ __le64 cmd_tbl; /* command table address */
__le64 open_frame; /* open addr frame address */ __le64 open_frame; /* open addr frame address */
__le64 status_buf; /* status buffer address */ __le64 status_buf; /* status buffer address */
__le64 prd_tbl; /* PRD tbl address */ __le64 prd_tbl; /* PRD tbl address */
@ -82,16 +202,17 @@ struct mvs_cmd_hdr {
struct mvs_port { struct mvs_port {
struct asd_sas_port sas_port; struct asd_sas_port sas_port;
u8 port_attached; u8 port_attached;
u8 taskfileset;
u8 wide_port_phymap; u8 wide_port_phymap;
struct list_head list; struct list_head list;
}; };
struct mvs_phy { struct mvs_phy {
struct mvs_info *mvi;
struct mvs_port *port; struct mvs_port *port;
struct asd_sas_phy sas_phy; struct asd_sas_phy sas_phy;
struct sas_identify identify; struct sas_identify identify;
struct scsi_device *sdev; struct scsi_device *sdev;
struct timer_list timer;
u64 dev_sas_addr; u64 dev_sas_addr;
u64 att_dev_sas_addr; u64 att_dev_sas_addr;
u32 att_dev_info; u32 att_dev_info;
@ -102,15 +223,34 @@ struct mvs_phy {
u32 frame_rcvd_size; u32 frame_rcvd_size;
u8 frame_rcvd[32]; u8 frame_rcvd[32];
u8 phy_attached; u8 phy_attached;
u8 phy_mode;
u8 reserved[2];
u32 phy_event;
enum sas_linkrate minimum_linkrate; enum sas_linkrate minimum_linkrate;
enum sas_linkrate maximum_linkrate; enum sas_linkrate maximum_linkrate;
}; };
struct mvs_device {
enum sas_dev_type dev_type;
struct domain_device *sas_device;
u32 attached_phy;
u32 device_id;
u32 runing_req;
u8 taskfileset;
u8 dev_status;
u16 reserved;
struct list_head dev_entry;
};
struct mvs_slot_info { struct mvs_slot_info {
struct list_head list; struct list_head entry;
struct sas_task *task; union {
struct sas_task *task;
void *tdata;
};
u32 n_elem; u32 n_elem;
u32 tx; u32 tx;
u32 slot_tag;
/* DMA buffer for storing cmd tbl, open addr frame, status buffer, /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
* and PRD table * and PRD table
@ -120,9 +260,10 @@ struct mvs_slot_info {
#if _MV_DUMP #if _MV_DUMP
u32 cmd_size; u32 cmd_size;
#endif #endif
void *response; void *response;
struct mvs_port *port; struct mvs_port *port;
struct mvs_device *device;
void *open_frame;
}; };
struct mvs_info { struct mvs_info {
@ -133,17 +274,17 @@ struct mvs_info {
/* our device */ /* our device */
struct pci_dev *pdev; struct pci_dev *pdev;
struct device *dev;
/* enhanced mode registers */ /* enhanced mode registers */
void __iomem *regs; void __iomem *regs;
/* peripheral registers */ /* peripheral or soc registers */
void __iomem *peri_regs; void __iomem *regs_ex;
u8 sas_addr[SAS_ADDR_SIZE]; u8 sas_addr[SAS_ADDR_SIZE];
/* SCSI/SAS glue */ /* SCSI/SAS glue */
struct sas_ha_struct sas; struct sas_ha_struct *sas;
struct Scsi_Host *shost; struct Scsi_Host *shost;
/* TX (delivery) DMA ring */ /* TX (delivery) DMA ring */
@ -154,7 +295,7 @@ struct mvs_info {
u32 tx_prod; u32 tx_prod;
/* RX (completion) DMA ring */ /* RX (completion) DMA ring */
__le32 *rx; __le32 *rx;
dma_addr_t rx_dma; dma_addr_t rx_dma;
/* RX consumer idx */ /* RX consumer idx */
@ -168,38 +309,98 @@ struct mvs_info {
struct mvs_cmd_hdr *slot; struct mvs_cmd_hdr *slot;
dma_addr_t slot_dma; dma_addr_t slot_dma;
u32 chip_id;
const struct mvs_chip_info *chip; const struct mvs_chip_info *chip;
u8 tags[MVS_SLOTS]; int tags_num;
struct mvs_slot_info slot_info[MVS_SLOTS]; u8 tags[MVS_SLOTS >> 3];
/* further per-slot information */
/* further per-slot information */
struct mvs_phy phy[MVS_MAX_PHYS]; struct mvs_phy phy[MVS_MAX_PHYS];
struct mvs_port port[MVS_MAX_PHYS]; struct mvs_port port[MVS_MAX_PHYS];
#ifdef MVS_USE_TASKLET u32 irq;
struct tasklet_struct tasklet; u32 exp_req;
u32 id;
u64 sata_reg_set;
struct list_head *hba_list;
struct list_head soc_entry;
struct list_head wq_list;
unsigned long instance;
u16 flashid;
u32 flashsize;
u32 flashsectSize;
void *addon;
struct mvs_device devices[MVS_MAX_DEVICES];
#ifndef DISABLE_HOTPLUG_DMA_FIX
void *bulk_buffer;
dma_addr_t bulk_buffer_dma;
#define TRASH_BUCKET_SIZE 0x20000
#endif #endif
struct mvs_slot_info slot_info[0];
}; };
struct mvs_prv_info{
u8 n_host;
u8 n_phy;
u16 reserve;
struct mvs_info *mvi[2];
};
struct mvs_wq {
struct delayed_work work_q;
struct mvs_info *mvi;
void *data;
int handler;
struct list_head entry;
};
struct mvs_task_exec_info {
struct sas_task *task;
struct mvs_cmd_hdr *hdr;
struct mvs_port *port;
u32 tag;
int n_elem;
};
/******************** function prototype *********************/
void mvs_get_sas_addr(void *buf, u32 buflen);
void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
void mvs_tag_free(struct mvs_info *mvi, u32 tag);
void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
void mvs_tag_init(struct mvs_info *mvi);
void mvs_iounmap(void __iomem *regs);
int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func, int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
void *funcdata); void *funcdata);
void __devinit mvs_set_sas_addr(struct mvs_info *mvi, int port_id,
u32 off_lo, u32 off_hi, u64 sas_addr);
int mvs_slave_alloc(struct scsi_device *scsi_dev);
int mvs_slave_configure(struct scsi_device *sdev); int mvs_slave_configure(struct scsi_device *sdev);
void mvs_scan_start(struct Scsi_Host *shost); void mvs_scan_start(struct Scsi_Host *shost);
int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time); int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags); int mvs_queue_command(struct sas_task *task, const int num,
int mvs_task_abort(struct sas_task *task); gfp_t gfp_flags);
int mvs_abort_task(struct sas_task *task);
int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
int mvs_clear_aca(struct domain_device *dev, u8 *lun);
int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
void mvs_port_formed(struct asd_sas_phy *sas_phy); void mvs_port_formed(struct asd_sas_phy *sas_phy);
void mvs_port_deformed(struct asd_sas_phy *sas_phy);
int mvs_dev_found(struct domain_device *dev);
void mvs_dev_gone(struct domain_device *dev);
int mvs_lu_reset(struct domain_device *dev, u8 *lun);
int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
int mvs_I_T_nexus_reset(struct domain_device *dev); int mvs_I_T_nexus_reset(struct domain_device *dev);
void mvs_int_full(struct mvs_info *mvi); int mvs_query_task(struct sas_task *task);
void mvs_tag_init(struct mvs_info *mvi); void mvs_release_task(struct mvs_info *mvi, int phy_no,
int mvs_nvram_read(struct mvs_info *mvi, u32 addr, void *buf, u32 buflen); struct domain_device *dev);
int __devinit mvs_hw_init(struct mvs_info *mvi); void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
void __devinit mvs_print_info(struct mvs_info *mvi); void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
void mvs_hba_interrupt_enable(struct mvs_info *mvi); int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
void mvs_hba_interrupt_disable(struct mvs_info *mvi); void mvs_hexdump(u32 size, u8 *data, u32 baseaddr);
void mvs_detect_porttype(struct mvs_info *mvi, int i);
u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port);
void mvs_enable_xmt(struct mvs_info *mvi, int PhyId);
void __devinit mvs_phy_hacks(struct mvs_info *mvi);
void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port);
#endif #endif