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ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support
Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings of Designware I2S controller. The I2S controller needs two reset items to work properly on the JH7110 SoC. And TX0 channel as master mode needs 5 clock items and TX1/RX channels as slave mode need 9 clock items on the JH7110 SoC. The RX channel needs System Register Controller property to enable it and other platforms do not need it. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230821144151.207339-2-xingyu.wu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -17,6 +17,9 @@ properties:
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- const: snps,designware-i2s
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- const: snps,designware-i2s
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- enum:
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- enum:
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- snps,designware-i2s
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- snps,designware-i2s
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- starfive,jh7110-i2stx0
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- starfive,jh7110-i2stx1
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- starfive,jh7110-i2srx
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reg:
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reg:
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maxItems: 1
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maxItems: 1
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@ -29,15 +32,36 @@ properties:
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maxItems: 1
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maxItems: 1
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clocks:
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clocks:
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description: Sampling rate reference clock
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items:
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maxItems: 1
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- description: Sampling rate reference clock
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- description: APB clock
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- description: Audio master clock
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- description: Inner audio master clock source
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- description: External audio master clock source
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- description: Bit clock
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- description: Left/right channel clock
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- description: External bit clock
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- description: External left/right channel clock
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minItems: 1
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clock-names:
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clock-names:
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const: i2sclk
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items:
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- const: i2sclk
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- const: apb
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- const: mclk
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- const: mclk_inner
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- const: mclk_ext
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- const: bclk
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- const: lrck
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- const: bclk_ext
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- const: lrck_ext
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minItems: 1
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resets:
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resets:
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items:
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items:
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- description: Optional controller resets
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- description: Optional controller resets
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- description: controller reset of Sampling rate
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minItems: 1
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dmas:
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dmas:
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items:
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items:
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@ -51,6 +75,17 @@ properties:
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- const: rx
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- const: rx
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minItems: 1
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minItems: 1
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starfive,syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to System Register Controller sys_syscon node.
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- description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
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- description: I2S-rx enabled control mask
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description:
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The phandle to System Register Controller syscon node and the I2S-rx(ADC)
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enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
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allOf:
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allOf:
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- $ref: dai-common.yaml#
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- $ref: dai-common.yaml#
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- if:
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- if:
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@ -66,6 +101,73 @@ allOf:
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properties:
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properties:
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"#sound-dai-cells":
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"#sound-dai-cells":
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const: 0
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const: 0
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- if:
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properties:
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compatible:
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contains:
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const: snps,designware-i2s
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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resets:
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maxItems: 1
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else:
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properties:
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resets:
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minItems: 2
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maxItems: 2
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- if:
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properties:
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compatible:
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contains:
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const: starfive,jh7110-i2stx0
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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minItems: 5
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maxItems: 5
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required:
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- resets
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- if:
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properties:
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compatible:
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contains:
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const: starfive,jh7110-i2stx1
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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minItems: 9
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maxItems: 9
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required:
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- resets
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- if:
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properties:
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compatible:
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contains:
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const: starfive,jh7110-i2srx
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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minItems: 9
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maxItems: 9
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required:
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- resets
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- starfive,syscon
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else:
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properties:
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starfive,syscon: false
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required:
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required:
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- compatible
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- compatible
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