ASoC: dt-bindings: snps,designware-i2s: Add StarFive JH7110 SoC support

Add the StarFive JH7110 (TX0/TX1/RX channel) SoC support in the bindings
of Designware I2S controller. The I2S controller needs two reset items
to work properly on the JH7110 SoC. And TX0 channel as master mode needs
5 clock items and TX1/RX channels as slave mode need 9 clock items on
the JH7110 SoC. The RX channel needs System Register Controller property
to enable it and other platforms do not need it.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230821144151.207339-2-xingyu.wu@starfivetech.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Xingyu Wu 2023-08-21 22:41:47 +08:00 committed by Mark Brown
parent 220adc0fda
commit 206110c74c
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@ -17,6 +17,9 @@ properties:
- const: snps,designware-i2s
- enum:
- snps,designware-i2s
- starfive,jh7110-i2stx0
- starfive,jh7110-i2stx1
- starfive,jh7110-i2srx
reg:
maxItems: 1
@ -29,15 +32,36 @@ properties:
maxItems: 1
clocks:
description: Sampling rate reference clock
maxItems: 1
items:
- description: Sampling rate reference clock
- description: APB clock
- description: Audio master clock
- description: Inner audio master clock source
- description: External audio master clock source
- description: Bit clock
- description: Left/right channel clock
- description: External bit clock
- description: External left/right channel clock
minItems: 1
clock-names:
const: i2sclk
items:
- const: i2sclk
- const: apb
- const: mclk
- const: mclk_inner
- const: mclk_ext
- const: bclk
- const: lrck
- const: bclk_ext
- const: lrck_ext
minItems: 1
resets:
items:
- description: Optional controller resets
- description: controller reset of Sampling rate
minItems: 1
dmas:
items:
@ -51,6 +75,17 @@ properties:
- const: rx
minItems: 1
starfive,syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to System Register Controller sys_syscon node.
- description: I2S-rx enabled control offset of SYS_SYSCONSAIF__SYSCFG register.
- description: I2S-rx enabled control mask
description:
The phandle to System Register Controller syscon node and the I2S-rx(ADC)
enabled control offset and mask of SYS_SYSCONSAIF__SYSCFG register.
allOf:
- $ref: dai-common.yaml#
- if:
@ -66,6 +101,73 @@ allOf:
properties:
"#sound-dai-cells":
const: 0
- if:
properties:
compatible:
contains:
const: snps,designware-i2s
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
resets:
maxItems: 1
else:
properties:
resets:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
const: starfive,jh7110-i2stx0
then:
properties:
clocks:
minItems: 5
maxItems: 5
clock-names:
minItems: 5
maxItems: 5
required:
- resets
- if:
properties:
compatible:
contains:
const: starfive,jh7110-i2stx1
then:
properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
minItems: 9
maxItems: 9
required:
- resets
- if:
properties:
compatible:
contains:
const: starfive,jh7110-i2srx
then:
properties:
clocks:
minItems: 9
maxItems: 9
clock-names:
minItems: 9
maxItems: 9
required:
- resets
- starfive,syscon
else:
properties:
starfive,syscon: false
required:
- compatible