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x86: add new cache descriptor
The latest rev of Intel doc AP-485 details a new cache descriptor that we don't yet support. A 6MB 24-way assoc L2 cache. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -62,6 +62,7 @@ static struct _cache_table cache_table[] __cpuinitdata =
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{ 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
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{ 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
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{ 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
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{ 0x4e, LVL_2, 6144 }, /* 24-way set assoc, 64 byte line size */
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{ 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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