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x86: x86 ptrace getreg/putreg merge
This merges 64-bit support into the low-level register access functions in arch/x86/kernel/ptrace.c, paving the way to share this file between 32-bit and 64-bit builds. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Roland McGrath
Ingo Molnar
parent
06ee1b687a
commit
2047b08be6
@ -24,6 +24,8 @@
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#include <asm/debugreg.h>
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#include <asm/ldt.h>
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#include <asm/desc.h>
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#include <asm/prctl.h>
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#include <asm/proto.h>
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/*
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* does not yet catch signals sent when the child dies.
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@ -40,6 +42,16 @@
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X86_EFLAGS_DF | X86_EFLAGS_OF | \
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X86_EFLAGS_RF | X86_EFLAGS_AC))
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/*
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* Determines whether a value may be installed in a segment register.
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*/
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static inline bool invalid_selector(u16 value)
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{
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return unlikely(value != 0 && (value & SEGMENT_RPL_MASK) != USER_RPL);
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}
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#ifdef CONFIG_X86_32
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#define FLAG_MASK FLAG_MASK_32
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static long *pt_regs_access(struct pt_regs *regs, unsigned long regno)
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@ -73,7 +85,7 @@ static int set_segment_reg(struct task_struct *task,
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/*
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* The value argument was already truncated to 16 bits.
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*/
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if (value && (value & 3) != 3)
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if (invalid_selector(value))
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return -EIO;
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if (offset != offsetof(struct user_regs_struct, gs))
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@ -91,6 +103,142 @@ static int set_segment_reg(struct task_struct *task,
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return 0;
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}
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static unsigned long debugreg_addr_limit(struct task_struct *task)
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{
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return TASK_SIZE - 3;
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}
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#else /* CONFIG_X86_64 */
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#define FLAG_MASK (FLAG_MASK_32 | X86_EFLAGS_NT)
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static unsigned long *pt_regs_access(struct pt_regs *regs, unsigned long offset)
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{
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BUILD_BUG_ON(offsetof(struct pt_regs, r15) != 0);
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return ®s->r15 + (offset / sizeof(regs->r15));
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}
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static u16 get_segment_reg(struct task_struct *task, unsigned long offset)
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{
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/*
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* Returning the value truncates it to 16 bits.
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*/
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unsigned int seg;
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switch (offset) {
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case offsetof(struct user_regs_struct, fs):
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if (task == current) {
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/* Older gas can't assemble movq %?s,%r?? */
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asm("movl %%fs,%0" : "=r" (seg));
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return seg;
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}
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return task->thread.fsindex;
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case offsetof(struct user_regs_struct, gs):
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if (task == current) {
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asm("movl %%gs,%0" : "=r" (seg));
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return seg;
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}
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return task->thread.gsindex;
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case offsetof(struct user_regs_struct, ds):
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if (task == current) {
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asm("movl %%ds,%0" : "=r" (seg));
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return seg;
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}
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return task->thread.ds;
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case offsetof(struct user_regs_struct, es):
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if (task == current) {
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asm("movl %%es,%0" : "=r" (seg));
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return seg;
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}
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return task->thread.es;
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case offsetof(struct user_regs_struct, cs):
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case offsetof(struct user_regs_struct, ss):
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break;
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}
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return *pt_regs_access(task_pt_regs(task), offset);
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}
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static int set_segment_reg(struct task_struct *task,
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unsigned long offset, u16 value)
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{
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/*
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* The value argument was already truncated to 16 bits.
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*/
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if (invalid_selector(value))
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return -EIO;
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switch (offset) {
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case offsetof(struct user_regs_struct,fs):
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/*
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* If this is setting fs as for normal 64-bit use but
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* setting fs_base has implicitly changed it, leave it.
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*/
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if ((value == FS_TLS_SEL && task->thread.fsindex == 0 &&
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task->thread.fs != 0) ||
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(value == 0 && task->thread.fsindex == FS_TLS_SEL &&
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task->thread.fs == 0))
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break;
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task->thread.fsindex = value;
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if (task == current)
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loadsegment(fs, task->thread.fsindex);
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break;
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case offsetof(struct user_regs_struct,gs):
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/*
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* If this is setting gs as for normal 64-bit use but
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* setting gs_base has implicitly changed it, leave it.
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*/
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if ((value == GS_TLS_SEL && task->thread.gsindex == 0 &&
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task->thread.gs != 0) ||
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(value == 0 && task->thread.gsindex == GS_TLS_SEL &&
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task->thread.gs == 0))
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break;
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task->thread.gsindex = value;
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if (task == current)
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load_gs_index(task->thread.gsindex);
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break;
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case offsetof(struct user_regs_struct,ds):
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task->thread.ds = value;
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if (task == current)
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loadsegment(ds, task->thread.ds);
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break;
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case offsetof(struct user_regs_struct,es):
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task->thread.es = value;
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if (task == current)
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loadsegment(es, task->thread.es);
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break;
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/*
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* Can't actually change these in 64-bit mode.
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*/
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case offsetof(struct user_regs_struct,cs):
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#ifdef CONFIG_IA32_EMULATION
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if (test_tsk_thread_flag(task, TIF_IA32))
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task_pt_regs(task)->cs = value;
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break;
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#endif
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case offsetof(struct user_regs_struct,ss):
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#ifdef CONFIG_IA32_EMULATION
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if (test_tsk_thread_flag(task, TIF_IA32))
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task_pt_regs(task)->ss = value;
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break;
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#endif
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}
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return 0;
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}
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static unsigned long debugreg_addr_limit(struct task_struct *task)
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{
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#ifdef CONFIG_IA32_EMULATION
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if (test_tsk_thread_flag(task, TIF_IA32))
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return IA32_PAGE_OFFSET - 3;
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#endif
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return TASK_SIZE64 - 7;
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}
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#endif /* CONFIG_X86_32 */
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static unsigned long get_flags(struct task_struct *task)
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{
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unsigned long retval = task_pt_regs(task)->flags;
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@ -137,6 +285,29 @@ static int putreg(struct task_struct *child,
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case offsetof(struct user_regs_struct, flags):
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return set_flags(child, value);
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#ifdef CONFIG_X86_64
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case offsetof(struct user_regs_struct,fs_base):
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if (value >= TASK_SIZE_OF(child))
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return -EIO;
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/*
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* When changing the segment base, use do_arch_prctl
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* to set either thread.fs or thread.fsindex and the
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* corresponding GDT slot.
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*/
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if (child->thread.fs != value)
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return do_arch_prctl(child, ARCH_SET_FS, value);
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return 0;
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case offsetof(struct user_regs_struct,gs_base):
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/*
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* Exactly the same here as the %fs handling above.
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*/
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if (value >= TASK_SIZE_OF(child))
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return -EIO;
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if (child->thread.gs != value)
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return do_arch_prctl(child, ARCH_SET_GS, value);
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return 0;
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#endif
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}
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*pt_regs_access(task_pt_regs(child), offset) = value;
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@ -156,6 +327,37 @@ static unsigned long getreg(struct task_struct *task, unsigned long offset)
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case offsetof(struct user_regs_struct, flags):
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return get_flags(task);
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#ifdef CONFIG_X86_64
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case offsetof(struct user_regs_struct, fs_base): {
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/*
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* do_arch_prctl may have used a GDT slot instead of
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* the MSR. To userland, it appears the same either
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* way, except the %fs segment selector might not be 0.
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*/
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unsigned int seg = task->thread.fsindex;
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if (task->thread.fs != 0)
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return task->thread.fs;
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if (task == current)
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asm("movl %%fs,%0" : "=r" (seg));
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if (seg != FS_TLS_SEL)
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return 0;
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return get_desc_base(&task->thread.tls_array[FS_TLS]);
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}
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case offsetof(struct user_regs_struct, gs_base): {
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/*
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* Exactly the same here as the %fs handling above.
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*/
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unsigned int seg = task->thread.gsindex;
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if (task->thread.gs != 0)
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return task->thread.gs;
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if (task == current)
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asm("movl %%gs,%0" : "=r" (seg));
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if (seg != GS_TLS_SEL)
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return 0;
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return get_desc_base(&task->thread.tls_array[GS_TLS]);
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}
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#endif
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}
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return *pt_regs_access(task_pt_regs(task), offset);
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@ -187,7 +389,7 @@ static int ptrace_set_debugreg(struct task_struct *child,
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if (unlikely(n == 4 || n == 5))
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return -EIO;
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if (n < 4 && unlikely(data >= TASK_SIZE - 3))
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if (n < 4 && unlikely(data >= debugreg_addr_limit(child)))
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return -EIO;
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switch (n) {
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@ -197,6 +399,8 @@ static int ptrace_set_debugreg(struct task_struct *child,
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case 3: child->thread.debugreg3 = data; break;
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case 6:
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if ((data & ~0xffffffffUL) != 0)
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return -EIO;
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child->thread.debugreg6 = data;
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break;
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@ -215,7 +419,7 @@ static int ptrace_set_debugreg(struct task_struct *child,
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* data in the watchpoint case.
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*
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* The invalid values are:
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* - LENi == 0x10 (undefined), so mask |= 0x0f00.
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* - LENi == 0x10 (undefined), so mask |= 0x0f00. [32-bit]
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* - R/Wi == 0x10 (break on I/O reads or writes), so
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* mask |= 0x4444.
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* - R/Wi == 0x00 && LENi != 0x00, so we have mask |=
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@ -231,9 +435,14 @@ static int ptrace_set_debugreg(struct task_struct *child,
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* 64-bit kernel), so the x86_64 mask value is 0x5454.
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* See the AMD manual no. 24593 (AMD64 System Programming)
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*/
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#ifdef CONFIG_X86_32
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#define DR7_MASK 0x5f54
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#else
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#define DR7_MASK 0x5554
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#endif
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data &= ~DR_CONTROL_RESERVED;
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for (i = 0; i < 4; i++)
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if ((0x5f54 >> ((data >> (16 + 4*i)) & 0xf)) & 1)
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if ((DR7_MASK >> ((data >> (16 + 4*i)) & 0xf)) & 1)
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return -EIO;
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child->thread.debugreg7 = data;
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if (data)
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