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drm/amd/powerplay: support VCN powergate status retrieval on Raven
Enable VCN powergate status report on Raven. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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201cd702b7
@ -1111,6 +1111,7 @@ static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
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static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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void *value, int *size)
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{
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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uint32_t sclk, mclk;
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int ret = 0;
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@ -1132,6 +1133,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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case AMDGPU_PP_SENSOR_GPU_TEMP:
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*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
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break;
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case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
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*(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
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*size = 4;
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break;
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default:
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ret = -EINVAL;
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break;
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@ -1175,18 +1180,22 @@ static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
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static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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if (bgate) {
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_VCN,
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AMD_PG_STATE_GATE);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_PowerDownVcn, 0);
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smu10_data->vcn_power_gated = true;
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} else {
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_PowerUpVcn, 0);
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amdgpu_device_ip_set_powergating_state(hwmgr->adev,
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AMD_IP_BLOCK_TYPE_VCN,
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AMD_PG_STATE_UNGATE);
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smu10_data->vcn_power_gated = false;
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}
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}
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