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clk: rockchip: allow additional mux options for cpu-clock frequency changes

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In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
                         |--\
                         |   \            |--\
 --apll--|\              |    \           |   \
         | |--apll_core--|     \          |    \
 --24M---|/              |mux1 |--[gate]--|mux2|---clk_core
                         |     /          |    /
 --gpll--|\              |    /    |------|   /
         | |--gpll_core--|   /     |      |--/
 --24M---|/              |--/      |
                                   |
 -------apll_directly--------------|

When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".

However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"

So add pre_mux and post_mux options to cover this special requirements.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[rebase]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Elaine Zhang 2022-10-18 17:14:04 +02:00 committed by Heiko Stuebner
parent 8f6594494b
commit 2004b7b180
2 changed files with 43 additions and 0 deletions
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41
drivers/clk/rockchip/clk-cpu.c
View File

@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk,
}
}
static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate)
{
int i;
/* alternate parent is active now. set the pre_muxs */
for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
if (!clksel->reg)
break;
pr_debug("%s: setting reg 0x%x to 0x%x\n",
__func__, clksel->reg, clksel->val);
writel(clksel->val, cpuclk->reg_base + clksel->reg);
}
}
static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
const struct rockchip_cpuclk_rate_table *rate)
{
int i;
/* alternate parent is active now. set the muxs */
for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
if (!clksel->reg)
break;
pr_debug("%s: setting reg 0x%x to 0x%x\n",
__func__, clksel->reg, clksel->val);
writel(clksel->val, cpuclk->reg_base + clksel->reg);
}
}
static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
struct clk_notifier_data *ndata)
{
@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
cpuclk->reg_base + reg_data->core_reg[i]);
}
}
rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
/* select alternate parent */
if (reg_data->mux_core_reg)
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
reg_data->mux_core_shift),
cpuclk->reg_base + reg_data->core_reg[0]);
rockchip_cpuclk_set_post_muxs(cpuclk, rate);
/* remove dividers */
for (i = 0; i < reg_data->num_cores; i++) {
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],

2
drivers/clk/rockchip/clk.h
View File

@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel {
struct rockchip_cpuclk_rate_table {
unsigned long prate;
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
};
/**