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staging: comedi: cb_pcidas: tidy up ADC mux/control register
Rename this register and its bit defines so they have namespace associated with the driver. Use the BIT macro to define the bits. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -97,17 +97,20 @@
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#define PCIDAS_CTRL_LADFUL BIT(13) /* fifo overflow / clear */
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#define PCIDAS_CTRL_DAEMI BIT(14) /* dac fifo empty int status / clear */
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#define ADCMUX_CONT 2 /* ADC CHANNEL MUX AND CONTROL reg */
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#define BEGIN_SCAN(x) ((x) & 0xf)
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#define END_SCAN(x) (((x) & 0xf) << 4)
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#define GAIN_BITS(x) (((x) & 0x3) << 8)
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#define UNIP 0x800 /* Analog front-end unipolar mode */
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#define SE 0x400 /* Inputs in single-ended mode */
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#define PACER_MASK 0x3000 /* pacer source bits */
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#define PACER_INT 0x1000 /* int. pacer */
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#define PACER_EXT_FALL 0x2000 /* ext. falling edge */
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#define PACER_EXT_RISE 0x3000 /* ext. rising edge */
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#define EOC 0x4000 /* adc not busy */
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#define PCIDAS_AI_REG 0x02 /* ADC CHANNEL MUX AND CONTROL reg */
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#define PCIDAS_AI_FIRST(x) ((x) & 0xf)
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#define PCIDAS_AI_LAST(x) (((x) & 0xf) << 4)
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#define PCIDAS_AI_CHAN(x) (PCIDAS_AI_FIRST(x) | PCIDAS_AI_LAST(x))
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#define PCIDAS_AI_GAIN(x) (((x) & 0x3) << 8)
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#define PCIDAS_AI_SE BIT(10) /* Inputs in single-ended mode */
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#define PCIDAS_AI_UNIP BIT(11) /* Analog front-end unipolar mode */
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#define PCIDAS_AI_PACER(x) (((x) & 0x3) << 12)
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#define PCIDAS_AI_PACER_SW PCIDAS_AI_PACER(0) /* software pacer */
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#define PCIDAS_AI_PACER_INT PCIDAS_AI_PACER(1) /* int. pacer */
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#define PCIDAS_AI_PACER_EXTN PCIDAS_AI_PACER(2) /* ext. falling edge */
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#define PCIDAS_AI_PACER_EXTP PCIDAS_AI_PACER(3) /* ext. rising edge */
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#define PCIDAS_AI_PACER_MASK PCIDAS_AI_PACER(3) /* pacer source bits */
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#define PCIDAS_AI_EOC BIT(14) /* adc not busy */
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#define TRIG_CONTSTAT 4 /* TRIGGER CONTROL/STATUS register */
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#define SW_TRIGGER 0x1 /* software start trigger */
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@ -333,8 +336,8 @@ static int cb_pcidas_ai_eoc(struct comedi_device *dev,
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struct cb_pcidas_private *devpriv = dev->private;
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unsigned int status;
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status = inw(devpriv->pcibar1 + ADCMUX_CONT);
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if (status & EOC)
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status = inw(devpriv->pcibar1 + PCIDAS_AI_REG);
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if (status & PCIDAS_AI_EOC)
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return 0;
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return -EBUSY;
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}
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@ -361,14 +364,14 @@ static int cb_pcidas_ai_rinsn(struct comedi_device *dev,
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}
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/* set mux limits and gain */
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bits = BEGIN_SCAN(chan) | END_SCAN(chan) | GAIN_BITS(range);
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bits = PCIDAS_AI_CHAN(chan) | PCIDAS_AI_GAIN(range);
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/* set unipolar/bipolar */
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if (comedi_range_is_unipolar(s, range))
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bits |= UNIP;
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bits |= PCIDAS_AI_UNIP;
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/* set single-ended/differential */
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if (aref != AREF_DIFF)
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bits |= SE;
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outw(bits, devpriv->pcibar1 + ADCMUX_CONT);
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bits |= PCIDAS_AI_SE;
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outw(bits, devpriv->pcibar1 + PCIDAS_AI_REG);
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/* clear fifo */
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outw(0, devpriv->pcibar2 + PCIDAS_AI_FIFO_CLR_REG);
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@ -861,21 +864,21 @@ static int cb_pcidas_ai_cmd(struct comedi_device *dev,
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outw(0, devpriv->pcibar2 + PCIDAS_AI_FIFO_CLR_REG);
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/* set mux limits, gain and pacer source */
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bits = BEGIN_SCAN(CR_CHAN(cmd->chanlist[0])) |
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END_SCAN(CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])) |
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GAIN_BITS(range0);
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bits = PCIDAS_AI_FIRST(CR_CHAN(cmd->chanlist[0])) |
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PCIDAS_AI_LAST(CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])) |
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PCIDAS_AI_GAIN(range0);
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/* set unipolar/bipolar */
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if (comedi_range_is_unipolar(s, range0))
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bits |= UNIP;
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bits |= PCIDAS_AI_UNIP;
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/* set singleended/differential */
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if (CR_AREF(cmd->chanlist[0]) != AREF_DIFF)
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bits |= SE;
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bits |= PCIDAS_AI_SE;
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/* set pacer source */
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if (cmd->convert_src == TRIG_EXT || cmd->scan_begin_src == TRIG_EXT)
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bits |= PACER_EXT_RISE;
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bits |= PCIDAS_AI_PACER_EXTP;
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else
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bits |= PACER_INT;
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outw(bits, devpriv->pcibar1 + ADCMUX_CONT);
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bits |= PCIDAS_AI_PACER_INT;
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outw(bits, devpriv->pcibar1 + PCIDAS_AI_REG);
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/* load counters */
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if (cmd->scan_begin_src == TRIG_TIMER ||
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@ -1034,8 +1037,7 @@ static int cb_pcidas_cancel(struct comedi_device *dev,
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/* disable start trigger source and burst mode */
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outw(0, devpriv->pcibar1 + TRIG_CONTSTAT);
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/* software pacer source */
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outw(0, devpriv->pcibar1 + ADCMUX_CONT);
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outw(PCIDAS_AI_PACER_SW, devpriv->pcibar1 + PCIDAS_AI_REG);
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return 0;
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}
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