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ARM: EXYNOS: Remove mach/irqs.h header
Since Exynos now uses CONFIG_SPARSE_IRQ and all remaining users of this header has been fixed, we can safely remove it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa
Kukjin Kim
parent
6e726ea4f5
commit
1f893d60d2
@ -1,476 +0,0 @@
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/*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - IRQ definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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#include <plat/irqs.h>
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/* PPI: Private Peripheral Interrupt */
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#define IRQ_PPI(x) (x + 16)
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/* SPI: Shared Peripheral Interrupt */
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#define IRQ_SPI(x) (x + 32)
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/* COMBINER */
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#define MAX_IRQ_IN_COMBINER 8
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#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
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#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
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/* For EXYNOS4 and EXYNOS5 */
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#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
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/* For EXYNOS4 SoCs */
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#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
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#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
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#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
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#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
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#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
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#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
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#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
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#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
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#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
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#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
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#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
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#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
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#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
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#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
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#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
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#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
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#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
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#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
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#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
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#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
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#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
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#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
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#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
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#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
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#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
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#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
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#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
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#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
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#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
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#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
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#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
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#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
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#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
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#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
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#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
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#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
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#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
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#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
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#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
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#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
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#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
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#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
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#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
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#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
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#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
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#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
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#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
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#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
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#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
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#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
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#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
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#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
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#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
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#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
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#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
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#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
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#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
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#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
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#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
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#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
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#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
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#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
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#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
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#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
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#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
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#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
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#define EXYNOS4_IRQ_2D IRQ_SPI(89)
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#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
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#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
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#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
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#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
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#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
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#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
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#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
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#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
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#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
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#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
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#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
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#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
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#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
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#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
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#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
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#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
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#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
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#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
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#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
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#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
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#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
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#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
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#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
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#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
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#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
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#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
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#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
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#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
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#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
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#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
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#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
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#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
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#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
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#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
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#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
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#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
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#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
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#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
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#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
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#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
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#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
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#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
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#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
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#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
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#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
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#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
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#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
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#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
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#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
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#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
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#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
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#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
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#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
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#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
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#define EXYNOS4210_MAX_COMBINER_NR 16
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#define EXYNOS4212_MAX_COMBINER_NR 18
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#define EXYNOS4412_MAX_COMBINER_NR 20
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#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
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#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
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#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
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/*
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* For Compatibility:
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* the default is for EXYNOS4, and
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* for exynos5, should be re-mapped at function
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*/
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#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
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#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
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#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
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#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
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#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
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#define IRQ_WDT EXYNOS4_IRQ_WDT
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#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
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#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
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#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
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#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
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#define IRQ_IIC EXYNOS4_IRQ_IIC
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#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
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#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
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#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
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#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
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#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
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#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
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#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
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#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
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#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
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#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
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#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
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#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
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#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
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#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
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#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
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#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
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#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
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#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
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#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
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#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
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#define IRQ_JPEG EXYNOS4_IRQ_JPEG
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#define IRQ_2D EXYNOS4_IRQ_2D
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#define IRQ_MIXER EXYNOS4_IRQ_MIXER
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#define IRQ_HDMI EXYNOS4_IRQ_HDMI
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#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
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#define IRQ_MFC EXYNOS4_IRQ_MFC
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#define IRQ_SDO EXYNOS4_IRQ_SDO
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#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
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#define IRQ_ADC EXYNOS4_IRQ_ADC0
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#define IRQ_TC EXYNOS4_IRQ_PEN0
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#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
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#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
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#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
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#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
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#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
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#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
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/* For EXYNOS5 SoCs */
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#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
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#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
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#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
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#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
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#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
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#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
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#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
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#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
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#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
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#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
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#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
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#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
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#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
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#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
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#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
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#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
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#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
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#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
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#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
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#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
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#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
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#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
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#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
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#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
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#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
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#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
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#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
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#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
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#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
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#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
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#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
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#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
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#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
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#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
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#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
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#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
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#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
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#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
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#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
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#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
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#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
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#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
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#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
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#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
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#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
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#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
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#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
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#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
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#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
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#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
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#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
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#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
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#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
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#define EXYNOS5_IRQ_2D IRQ_SPI(91)
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#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
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#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
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#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
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#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
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#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
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#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
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#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
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#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
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#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
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#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
|
||||
#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
|
||||
#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
|
||||
#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
|
||||
#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
|
||||
#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
|
||||
#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
|
||||
#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
|
||||
#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
|
||||
#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
|
||||
#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
|
||||
#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
|
||||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
|
||||
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
|
||||
|
||||
/* EXYNOS5440 */
|
||||
|
||||
#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
|
||||
#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
|
||||
|
||||
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
|
||||
|
||||
#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
|
||||
|
||||
#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
|
||||
#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
|
||||
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
|
||||
#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
|
||||
#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
|
||||
#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
|
||||
#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
|
||||
#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
|
||||
#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
|
||||
#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
|
||||
#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
|
||||
#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
|
||||
#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
|
||||
|
||||
#define EXYNOS5_MAX_COMBINER_NR 32
|
||||
|
||||
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
|
||||
#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
|
||||
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
|
||||
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
|
||||
|
||||
#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
|
||||
EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
|
||||
|
||||
#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
|
||||
#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
|
||||
#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
|
||||
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
|
||||
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
|
||||
|
||||
#ifndef CONFIG_SPARSE_IRQ
|
||||
#define NR_IRQS EXYNOS_NR_IRQS
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IRQS_H */
|
||||
Loading…
Reference in New Issue
Block a user