Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-27 22:51:35 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM: mach-bcm: bcm281xx clock driver

Browse Source 
This pull request contains the Broadcom bcm281xx
 clock driver series. This series is being merged
 through the arm-soc tree because there is an
 ordering dependency where the driver *must* be
 merged before the related dts changes. This is
 a result of the bcm281xx dts already containing
 dummy fixed clock nodes that must be updated.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJTF/mHAAoJEOfTILNwq7R4+UAP/2JgHOHrwGX1RnGHO+1JY+0M
 N6fW/u9QJ9gV9wTH6vd5mBZisud5JhL8bpec0zobWeEYMpz6/MqVkMv9ilpOpuGU
 2Ol20l7mZibsG8R96yaDL4jy4Ddz84exXLUEug0Asvh6RGPRLC8YK28zjf7nRJkZ
 it7+yvTKQvmKgc1ATizKCzDJUFRqx2ZWnwmLlrtkP5gLB8pD2Qwe74V6h85BiIWC
 OFN0CpuOVAmwj9hQjU7kXY6jDOwMaDTBruJzrmLx4DrMIIrliOeOdI4Y9LMyL/Ih
 jqY3CCcfpjZf6MVu5WplD/Njv00OhFKSpfO/M9mH2IAlzcPl/ekjacqpyaSlkLAW
 l9bjctQFJslk95UYC2GFrLd6BmoMtY73ZDruDFYEhwEmdYUiSxuliOHhqDM/h1Y7
 m8Tx2zyToA6O0Voamq66/iy9LAoyjWBvSMGw7DYDp7yJ1WEB2Zz3TJHfkDLIxUWi
 ZSfvJxuKjCXimxQgQ/+pMomDFKNgWS7Z5Fe1HqSZnI7XAtAd12zmFExaIR0W25D6
 u5R4bdTibLMPdJ9zxA2OKUhedB/BGk6bd1rv0jEvmfGV5hJGAYLw9J/D0n3qs57F
 DffaVmh9uMv/AFbRBWWZUdwt3Qb38qPOiJo3E2d1txwpJ8hoNJOdJT3V1+WkAwQN
 8WYEMYj5k0yTUob523im
 =Kma/
 -----END PGP SIGNATURE-----

Merge tag 'armsoc/for-3.15/drivers' of git://github.com/broadcom/mach-bcm into next/drivers

Merge "ARM: mach-bcm: bcm281xx clock driver" from Matt Porter:

This pull request contains the Broadcom bcm281xx
clock driver series. This series is being merged
through the arm-soc tree because there is an
ordering dependency where the driver *must* be
merged before the related dts changes. This is
a result of the bcm281xx dts already containing
dummy fixed clock nodes that must be updated.

* tag 'armsoc/for-3.15/drivers' of git://github.com/broadcom/mach-bcm:
  clk: bcm281xx: don't disable unused peripheral clocks
  clk: bcm281xx: add initial clock framework support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-03-06 05:53:03 +01:00
commit 1f6e3763d0
9 changed files with 2707 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/clk/Kconfig
View File

@ -111,4 +111,5 @@ source "drivers/clk/qcom/Kconfig"
endmenu
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/mvebu/Kconfig"

1
drivers/clk/Makefile
View File

@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
ifeq ($(CONFIG_COMMON_CLK), y)

9
drivers/clk/bcm/Kconfig Normal file
View File

@ -0,0 +1,9 @@
config CLK_BCM_KONA
bool "Broadcom Kona CCU clock support"
depends on ARCH_BCM_MOBILE
depends on COMMON_CLK
default y
help
Enable common clock framework support for Broadcom SoCs
using "Kona" style clock control units, including those
in the BCM281xx family.

3
drivers/clk/bcm/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o

416
drivers/clk/bcm/clk-bcm281xx.c Normal file
View File

@ -0,0 +1,416 @@
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "clk-kona.h"
#include "dt-bindings/clock/bcm281xx.h"
/* bcm11351 CCU device tree "compatible" strings */
#define BCM11351_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
#define BCM11351_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
#define BCM11351_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
#define BCM11351_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
#define BCM11351_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
/* Root CCU clocks */
static struct peri_clk_data frac_1m_data = {
.gate = HW_SW_GATE(0x214, 16, 0, 1),
.trig = TRIGGER(0x0e04, 0),
.div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
.clocks = CLOCKS("ref_crystal"),
};
/* AON CCU clocks */
static struct peri_clk_data hub_timer_data = {
.gate = HW_SW_GATE(0x0414, 16, 0, 1),
.clocks = CLOCKS("bbl_32k",
"frac_1m",
"dft_19_5m"),
.sel = SELECTOR(0x0a10, 0, 2),
.trig = TRIGGER(0x0a40, 4),
};
static struct peri_clk_data pmu_bsc_data = {
.gate = HW_SW_GATE(0x0418, 16, 0, 1),
.clocks = CLOCKS("ref_crystal",
"pmu_bsc_var",
"bbl_32k"),
.sel = SELECTOR(0x0a04, 0, 2),
.div = DIVIDER(0x0a04, 3, 4),
.trig = TRIGGER(0x0a40, 0),
};
static struct peri_clk_data pmu_bsc_var_data = {
.clocks = CLOCKS("var_312m",
"ref_312m"),
.sel = SELECTOR(0x0a00, 0, 2),
.div = DIVIDER(0x0a00, 4, 5),
.trig = TRIGGER(0x0a40, 2),
};
/* Hub CCU clocks */
static struct peri_clk_data tmon_1m_data = {
.gate = HW_SW_GATE(0x04a4, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"frac_1m"),
.sel = SELECTOR(0x0e74, 0, 2),
.trig = TRIGGER(0x0e84, 1),
};
/* Master CCU clocks */
static struct peri_clk_data sdio1_data = {
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a28, 0, 3),
.div = DIVIDER(0x0a28, 4, 14),
.trig = TRIGGER(0x0afc, 9),
};
static struct peri_clk_data sdio2_data = {
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a2c, 0, 3),
.div = DIVIDER(0x0a2c, 4, 14),
.trig = TRIGGER(0x0afc, 10),
};
static struct peri_clk_data sdio3_data = {
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a34, 0, 3),
.div = DIVIDER(0x0a34, 4, 14),
.trig = TRIGGER(0x0afc, 12),
};
static struct peri_clk_data sdio4_data = {
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a30, 0, 3),
.div = DIVIDER(0x0a30, 4, 14),
.trig = TRIGGER(0x0afc, 11),
};
static struct peri_clk_data usb_ic_data = {
.gate = HW_SW_GATE(0x0354, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_96m",
"ref_96m"),
.div = FIXED_DIVIDER(2),
.sel = SELECTOR(0x0a24, 0, 2),
.trig = TRIGGER(0x0afc, 7),
};
/* also called usbh_48m */
static struct peri_clk_data hsic2_48m_data = {
.gate = HW_SW_GATE(0x0370, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a38, 0, 2),
.div = FIXED_DIVIDER(2),
.trig = TRIGGER(0x0afc, 5),
};
/* also called usbh_12m */
static struct peri_clk_data hsic2_12m_data = {
.gate = HW_SW_GATE(0x0370, 20, 4, 5),
.div = DIVIDER(0x0a38, 12, 2),
.clocks = CLOCKS("ref_crystal",
"var_96m",
"ref_96m"),
.pre_div = FIXED_DIVIDER(2),
.sel = SELECTOR(0x0a38, 0, 2),
.trig = TRIGGER(0x0afc, 5),
};
/* Slave CCU clocks */
static struct peri_clk_data uartb_data = {
.gate = HW_SW_GATE(0x0400, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_156m",
"ref_156m"),
.sel = SELECTOR(0x0a10, 0, 2),
.div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
.trig = TRIGGER(0x0afc, 2),
};
static struct peri_clk_data uartb2_data = {
.gate = HW_SW_GATE(0x0404, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_156m",
"ref_156m"),
.sel = SELECTOR(0x0a14, 0, 2),
.div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
.trig = TRIGGER(0x0afc, 3),
};
static struct peri_clk_data uartb3_data = {
.gate = HW_SW_GATE(0x0408, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_156m",
"ref_156m"),
.sel = SELECTOR(0x0a18, 0, 2),
.div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
.trig = TRIGGER(0x0afc, 4),
};
static struct peri_clk_data uartb4_data = {
.gate = HW_SW_GATE(0x0408, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_156m",
"ref_156m"),
.sel = SELECTOR(0x0a1c, 0, 2),
.div = FRAC_DIVIDER(0x0a1c, 4, 12, 8),
.trig = TRIGGER(0x0afc, 5),
};
static struct peri_clk_data ssp0_data = {
.gate = HW_SW_GATE(0x0410, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a20, 0, 3),
.div = DIVIDER(0x0a20, 4, 14),
.trig = TRIGGER(0x0afc, 6),
};
static struct peri_clk_data ssp2_data = {
.gate = HW_SW_GATE(0x0418, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a28, 0, 3),
.div = DIVIDER(0x0a28, 4, 14),
.trig = TRIGGER(0x0afc, 8),
};
static struct peri_clk_data bsc1_data = {
.gate = HW_SW_GATE(0x0458, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a64, 0, 3),
.trig = TRIGGER(0x0afc, 23),
};
static struct peri_clk_data bsc2_data = {
.gate = HW_SW_GATE(0x045c, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a68, 0, 3),
.trig = TRIGGER(0x0afc, 24),
};
static struct peri_clk_data bsc3_data = {
.gate = HW_SW_GATE(0x0484, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a84, 0, 3),
.trig = TRIGGER(0x0b00, 2),
};
static struct peri_clk_data pwm_data = {
.gate = HW_SW_GATE(0x0468, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m"),
.sel = SELECTOR(0x0a70, 0, 2),
.div = DIVIDER(0x0a70, 4, 3),
.trig = TRIGGER(0x0afc, 15),
};
/*
* CCU setup routines
*
* These are called from kona_dt_ccu_setup() to initialize the array
* of clocks provided by the CCU. Once allocated, the entries in
* the array are initialized by calling kona_clk_setup() with the
* initialization data for each clock. They return 0 if successful
* or an error code otherwise.
*/
static int __init bcm281xx_root_ccu_clks_setup(struct ccu_data *ccu)
{
struct clk **clks;
size_t count = BCM281XX_ROOT_CCU_CLOCK_COUNT;
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
if (!clks) {
pr_err("%s: failed to allocate root clocks\n", __func__);
return -ENOMEM;
}
ccu->data.clks = clks;
ccu->data.clk_num = count;
PERI_CLK_SETUP(clks, ccu, BCM281XX_ROOT_CCU_FRAC_1M, frac_1m);
return 0;
}
static int __init bcm281xx_aon_ccu_clks_setup(struct ccu_data *ccu)
{
struct clk **clks;
size_t count = BCM281XX_AON_CCU_CLOCK_COUNT;
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
if (!clks) {
pr_err("%s: failed to allocate aon clocks\n", __func__);
return -ENOMEM;
}
ccu->data.clks = clks;
ccu->data.clk_num = count;
PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_HUB_TIMER, hub_timer);
PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC, pmu_bsc);
PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC_VAR, pmu_bsc_var);
return 0;
}
static int __init bcm281xx_hub_ccu_clks_setup(struct ccu_data *ccu)
{
struct clk **clks;
size_t count = BCM281XX_HUB_CCU_CLOCK_COUNT;
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
if (!clks) {
pr_err("%s: failed to allocate hub clocks\n", __func__);
return -ENOMEM;
}
ccu->data.clks = clks;
ccu->data.clk_num = count;
PERI_CLK_SETUP(clks, ccu, BCM281XX_HUB_CCU_TMON_1M, tmon_1m);
return 0;
}
static int __init bcm281xx_master_ccu_clks_setup(struct ccu_data *ccu)
{
struct clk **clks;
size_t count = BCM281XX_MASTER_CCU_CLOCK_COUNT;
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
if (!clks) {
pr_err("%s: failed to allocate master clocks\n", __func__);
return -ENOMEM;
}
ccu->data.clks = clks;
ccu->data.clk_num = count;
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO1, sdio1);
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO2, sdio2);
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO3, sdio3);
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO4, sdio4);
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_USB_IC, usb_ic);
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_48M, hsic2_48m);
PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_12M, hsic2_12m);
return 0;
}
static int __init bcm281xx_slave_ccu_clks_setup(struct ccu_data *ccu)
{
struct clk **clks;
size_t count = BCM281XX_SLAVE_CCU_CLOCK_COUNT;
clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
if (!clks) {
pr_err("%s: failed to allocate slave clocks\n", __func__);
return -ENOMEM;
}
ccu->data.clks = clks;
ccu->data.clk_num = count;
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB, uartb);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB2, uartb2);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB3, uartb3);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB4, uartb4);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP0, ssp0);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP2, ssp2);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC1, bsc1);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC2, bsc2);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC3, bsc3);
PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_PWM, pwm);
return 0;
}
/* Device tree match table callback functions */
static void __init kona_dt_root_ccu_setup(struct device_node *node)
{
kona_dt_ccu_setup(node, bcm281xx_root_ccu_clks_setup);
}
static void __init kona_dt_aon_ccu_setup(struct device_node *node)
{
kona_dt_ccu_setup(node, bcm281xx_aon_ccu_clks_setup);
}
static void __init kona_dt_hub_ccu_setup(struct device_node *node)
{
kona_dt_ccu_setup(node, bcm281xx_hub_ccu_clks_setup);
}
static void __init kona_dt_master_ccu_setup(struct device_node *node)
{
kona_dt_ccu_setup(node, bcm281xx_master_ccu_clks_setup);
}
static void __init kona_dt_slave_ccu_setup(struct device_node *node)
{
kona_dt_ccu_setup(node, bcm281xx_slave_ccu_clks_setup);
}
CLK_OF_DECLARE(bcm11351_root_ccu, BCM11351_DT_ROOT_CCU_COMPAT,
kona_dt_root_ccu_setup);
CLK_OF_DECLARE(bcm11351_aon_ccu, BCM11351_DT_AON_CCU_COMPAT,
kona_dt_aon_ccu_setup);
CLK_OF_DECLARE(bcm11351_hub_ccu, BCM11351_DT_HUB_CCU_COMPAT,
kona_dt_hub_ccu_setup);
CLK_OF_DECLARE(bcm11351_master_ccu, BCM11351_DT_MASTER_CCU_COMPAT,
kona_dt_master_ccu_setup);
CLK_OF_DECLARE(bcm11351_slave_ccu, BCM11351_DT_SLAVE_CCU_COMPAT,
kona_dt_slave_ccu_setup);

769
drivers/clk/bcm/clk-kona-setup.c Normal file
View File

@ -0,0 +1,769 @@
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/io.h>
#include <linux/of_address.h>
#include "clk-kona.h"
/* These are used when a selector or trigger is found to be unneeded */
#define selector_clear_exists(sel) ((sel)->width = 0)
#define trigger_clear_exists(trig) FLAG_CLEAR(trig, TRIG, EXISTS)
LIST_HEAD(ccu_list); /* The list of set up CCUs */
/* Validity checking */
static bool clk_requires_trigger(struct kona_clk *bcm_clk)
{
struct peri_clk_data *peri = bcm_clk->peri;
struct bcm_clk_sel *sel;
struct bcm_clk_div *div;
if (bcm_clk->type != bcm_clk_peri)
return false;
sel = &peri->sel;
if (sel->parent_count && selector_exists(sel))
return true;
div = &peri->div;
if (!divider_exists(div))
return false;
/* Fixed dividers don't need triggers */
if (!divider_is_fixed(div))
return true;
div = &peri->pre_div;
return divider_exists(div) && !divider_is_fixed(div);
}
static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk)
{
struct peri_clk_data *peri;
struct bcm_clk_gate *gate;
struct bcm_clk_div *div;
struct bcm_clk_sel *sel;
struct bcm_clk_trig *trig;
const char *name;
u32 range;
u32 limit;
BUG_ON(bcm_clk->type != bcm_clk_peri);
peri = bcm_clk->peri;
name = bcm_clk->name;
range = bcm_clk->ccu->range;
limit = range - sizeof(u32);
limit = round_down(limit, sizeof(u32));
gate = &peri->gate;
if (gate_exists(gate)) {
if (gate->offset > limit) {
pr_err("%s: bad gate offset for %s (%u > %u)\n",
__func__, name, gate->offset, limit);
return false;
}
}
div = &peri->div;
if (divider_exists(div)) {
if (div->offset > limit) {
pr_err("%s: bad divider offset for %s (%u > %u)\n",
__func__, name, div->offset, limit);
return false;
}
}
div = &peri->pre_div;
if (divider_exists(div)) {
if (div->offset > limit) {
pr_err("%s: bad pre-divider offset for %s "
"(%u > %u)\n",
__func__, name, div->offset, limit);
return false;
}
}
sel = &peri->sel;
if (selector_exists(sel)) {
if (sel->offset > limit) {
pr_err("%s: bad selector offset for %s (%u > %u)\n",
__func__, name, sel->offset, limit);
return false;
}
}
trig = &peri->trig;
if (trigger_exists(trig)) {
if (trig->offset > limit) {
pr_err("%s: bad trigger offset for %s (%u > %u)\n",
__func__, name, trig->offset, limit);
return false;
}
}
trig = &peri->pre_trig;
if (trigger_exists(trig)) {
if (trig->offset > limit) {
pr_err("%s: bad pre-trigger offset for %s (%u > %u)\n",
__func__, name, trig->offset, limit);
return false;
}
}
return true;
}
/* A bit position must be less than the number of bits in a 32-bit register. */
static bool bit_posn_valid(u32 bit_posn, const char *field_name,
const char *clock_name)
{
u32 limit = BITS_PER_BYTE * sizeof(u32) - 1;
if (bit_posn > limit) {
pr_err("%s: bad %s bit for %s (%u > %u)\n", __func__,
field_name, clock_name, bit_posn, limit);
return false;
}
return true;
}
/*
* A bitfield must be at least 1 bit wide. Both the low-order and
* high-order bits must lie within a 32-bit register. We require
* fields to be less than 32 bits wide, mainly because we use
* shifting to produce field masks, and shifting a full word width
* is not well-defined by the C standard.
*/
static bool bitfield_valid(u32 shift, u32 width, const char *field_name,
const char *clock_name)
{
u32 limit = BITS_PER_BYTE * sizeof(u32);
if (!width) {
pr_err("%s: bad %s field width 0 for %s\n", __func__,
field_name, clock_name);
return false;
}
if (shift + width > limit) {
pr_err("%s: bad %s for %s (%u + %u > %u)\n", __func__,
field_name, clock_name, shift, width, limit);
return false;
}
return true;
}
/*
* All gates, if defined, have a status bit, and for hardware-only
* gates, that's it. Gates that can be software controlled also
* have an enable bit. And a gate that can be hardware or software
* controlled will have a hardware/software select bit.
*/
static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name,
const char *clock_name)
{
if (!bit_posn_valid(gate->status_bit, "gate status", clock_name))
return false;
if (gate_is_sw_controllable(gate)) {
if (!bit_posn_valid(gate->en_bit, "gate enable", clock_name))
return false;
if (gate_is_hw_controllable(gate)) {
if (!bit_posn_valid(gate->hw_sw_sel_bit,
"gate hw/sw select",
clock_name))
return false;
}
} else {
BUG_ON(!gate_is_hw_controllable(gate));
}
return true;
}
/*
* A selector bitfield must be valid. Its parent_sel array must
* also be reasonable for the field.
*/
static bool sel_valid(struct bcm_clk_sel *sel, const char *field_name,
const char *clock_name)
{
if (!bitfield_valid(sel->shift, sel->width, field_name, clock_name))
return false;
if (sel->parent_count) {
u32 max_sel;
u32 limit;
/*
* Make sure the selector field can hold all the
* selector values we expect to be able to use. A
* clock only needs to have a selector defined if it
* has more than one parent. And in that case the
* highest selector value will be in the last entry
* in the array.
*/
max_sel = sel->parent_sel[sel->parent_count - 1];
limit = (1 << sel->width) - 1;
if (max_sel > limit) {
pr_err("%s: bad selector for %s "
"(%u needs > %u bits)\n",
__func__, clock_name, max_sel,
sel->width);
return false;
}
} else {
pr_warn("%s: ignoring selector for %s (no parents)\n",
__func__, clock_name);
selector_clear_exists(sel);
kfree(sel->parent_sel);
sel->parent_sel = NULL;
}
return true;
}
/*
* A fixed divider just needs to be non-zero. A variable divider
* has to have a valid divider bitfield, and if it has a fraction,
* the width of the fraction must not be no more than the width of
* the divider as a whole.
*/
static bool div_valid(struct bcm_clk_div *div, const char *field_name,
const char *clock_name)
{
if (divider_is_fixed(div)) {
/* Any fixed divider value but 0 is OK */
if (div->fixed == 0) {
pr_err("%s: bad %s fixed value 0 for %s\n", __func__,
field_name, clock_name);
return false;
}
return true;
}
if (!bitfield_valid(div->shift, div->width, field_name, clock_name))
return false;
if (divider_has_fraction(div))
if (div->frac_width > div->width) {
pr_warn("%s: bad %s fraction width for %s (%u > %u)\n",
__func__, field_name, clock_name,
div->frac_width, div->width);
return false;
}
return true;
}
/*
* If a clock has two dividers, the combined number of fractional
* bits must be representable in a 32-bit unsigned value. This
* is because we scale up a dividend using both dividers before
* dividing to improve accuracy, and we need to avoid overflow.
*/
static bool kona_dividers_valid(struct kona_clk *bcm_clk)
{
struct peri_clk_data *peri = bcm_clk->peri;
struct bcm_clk_div *div;
struct bcm_clk_div *pre_div;
u32 limit;
BUG_ON(bcm_clk->type != bcm_clk_peri);
if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div))
return true;
div = &peri->div;
pre_div = &peri->pre_div;
if (divider_is_fixed(div) || divider_is_fixed(pre_div))
return true;
limit = BITS_PER_BYTE * sizeof(u32);
return div->frac_width + pre_div->frac_width <= limit;
}
/* A trigger just needs to represent a valid bit position */
static bool trig_valid(struct bcm_clk_trig *trig, const char *field_name,
const char *clock_name)
{
return bit_posn_valid(trig->bit, field_name, clock_name);
}
/* Determine whether the set of peripheral clock registers are valid. */
static bool
peri_clk_data_valid(struct kona_clk *bcm_clk)
{
struct peri_clk_data *peri;
struct bcm_clk_gate *gate;
struct bcm_clk_sel *sel;
struct bcm_clk_div *div;
struct bcm_clk_div *pre_div;
struct bcm_clk_trig *trig;
const char *name;
BUG_ON(bcm_clk->type != bcm_clk_peri);
/*
* First validate register offsets. This is the only place
* where we need something from the ccu, so we do these
* together.
*/
if (!peri_clk_data_offsets_valid(bcm_clk))
return false;
peri = bcm_clk->peri;
name = bcm_clk->name;
gate = &peri->gate;
if (gate_exists(gate) && !gate_valid(gate, "gate", name))
return false;
sel = &peri->sel;
if (selector_exists(sel)) {
if (!sel_valid(sel, "selector", name))
return false;
} else if (sel->parent_count > 1) {
pr_err("%s: multiple parents but no selector for %s\n",
__func__, name);
return false;
}
div = &peri->div;
pre_div = &peri->pre_div;
if (divider_exists(div)) {
if (!div_valid(div, "divider", name))
return false;
if (divider_exists(pre_div))
if (!div_valid(pre_div, "pre-divider", name))
return false;
} else if (divider_exists(pre_div)) {
pr_err("%s: pre-divider but no divider for %s\n", __func__,
name);
return false;
}
trig = &peri->trig;
if (trigger_exists(trig)) {
if (!trig_valid(trig, "trigger", name))
return false;
if (trigger_exists(&peri->pre_trig)) {
if (!trig_valid(trig, "pre-trigger", name)) {
return false;
}
}
if (!clk_requires_trigger(bcm_clk)) {
pr_warn("%s: ignoring trigger for %s (not needed)\n",
__func__, name);
trigger_clear_exists(trig);
}
} else if (trigger_exists(&peri->pre_trig)) {
pr_err("%s: pre-trigger but no trigger for %s\n", __func__,
name);
return false;
} else if (clk_requires_trigger(bcm_clk)) {
pr_err("%s: required trigger missing for %s\n", __func__,
name);
return false;
}
return kona_dividers_valid(bcm_clk);
}
static bool kona_clk_valid(struct kona_clk *bcm_clk)
{
switch (bcm_clk->type) {
case bcm_clk_peri:
if (!peri_clk_data_valid(bcm_clk))
return false;
break;
default:
pr_err("%s: unrecognized clock type (%d)\n", __func__,
(int)bcm_clk->type);
return false;
}
return true;
}
/*
* Scan an array of parent clock names to determine whether there
* are any entries containing BAD_CLK_NAME. Such entries are
* placeholders for non-supported clocks. Keep track of the
* position of each clock name in the original array.
*
* Allocates an array of pointers to to hold the names of all
* non-null entries in the original array, and returns a pointer to
* that array in *names. This will be used for registering the
* clock with the common clock code. On successful return,
* *count indicates how many entries are in that names array.
*
* If there is more than one entry in the resulting names array,
* another array is allocated to record the parent selector value
* for each (defined) parent clock. This is the value that
* represents this parent clock in the clock's source selector
* register. The position of the clock in the original parent array
* defines that selector value. The number of entries in this array
* is the same as the number of entries in the parent names array.
*
* The array of selector values is returned. If the clock has no
* parents, no selector is required and a null pointer is returned.
*
* Returns a null pointer if the clock names array supplied was
* null. (This is not an error.)
*
* Returns a pointer-coded error if an error occurs.
*/
static u32 *parent_process(const char *clocks[],
u32 *count, const char ***names)
{
static const char **parent_names;
static u32 *parent_sel;
const char **clock;
u32 parent_count;
u32 bad_count = 0;
u32 orig_count;
u32 i;
u32 j;
*count = 0; /* In case of early return */
*names = NULL;
if (!clocks)
return NULL;
/*
* Count the number of names in the null-terminated array,
* and find out how many of those are actually clock names.
*/
for (clock = clocks; *clock; clock++)
if (*clock == BAD_CLK_NAME)
bad_count++;
orig_count = (u32)(clock - clocks);
parent_count = orig_count - bad_count;
/* If all clocks are unsupported, we treat it as no clock */
if (!parent_count)
return NULL;
/* Avoid exceeding our parent clock limit */
if (parent_count > PARENT_COUNT_MAX) {
pr_err("%s: too many parents (%u > %u)\n", __func__,
parent_count, PARENT_COUNT_MAX);
return ERR_PTR(-EINVAL);
}
/*
* There is one parent name for each defined parent clock.
* We also maintain an array containing the selector value
* for each defined clock. If there's only one clock, the
* selector is not required, but we allocate space for the
* array anyway to keep things simple.
*/
parent_names = kmalloc(parent_count * sizeof(parent_names), GFP_KERNEL);
if (!parent_names) {
pr_err("%s: error allocating %u parent names\n", __func__,
parent_count);
return ERR_PTR(-ENOMEM);
}
/* There is at least one parent, so allocate a selector array */
parent_sel = kmalloc(parent_count * sizeof(*parent_sel), GFP_KERNEL);
if (!parent_sel) {
pr_err("%s: error allocating %u parent selectors\n", __func__,
parent_count);
kfree(parent_names);
return ERR_PTR(-ENOMEM);
}
/* Now fill in the parent names and selector arrays */
for (i = 0, j = 0; i < orig_count; i++) {
if (clocks[i] != BAD_CLK_NAME) {
parent_names[j] = clocks[i];
parent_sel[j] = i;
j++;
}
}
*names = parent_names;
*count = parent_count;
return parent_sel;
}
static int
clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel,
struct clk_init_data *init_data)
{
const char **parent_names = NULL;
u32 parent_count = 0;
u32 *parent_sel;
/*
* If a peripheral clock has multiple parents, the value
* used by the hardware to select that parent is represented
* by the parent clock's position in the "clocks" list. Some
* values don't have defined or supported clocks; these will
* have BAD_CLK_NAME entries in the parents[] array. The
* list is terminated by a NULL entry.
*
* We need to supply (only) the names of defined parent
* clocks when registering a clock though, so we use an
* array of parent selector values to map between the
* indexes the common clock code uses and the selector
* values we need.
*/
parent_sel = parent_process(clocks, &parent_count, &parent_names);
if (IS_ERR(parent_sel)) {
int ret = PTR_ERR(parent_sel);
pr_err("%s: error processing parent clocks for %s (%d)\n",
__func__, init_data->name, ret);
return ret;
}
init_data->parent_names = parent_names;
init_data->num_parents = parent_count;
sel->parent_count = parent_count;
sel->parent_sel = parent_sel;
return 0;
}
static void clk_sel_teardown(struct bcm_clk_sel *sel,
struct clk_init_data *init_data)
{
kfree(sel->parent_sel);
sel->parent_sel = NULL;
sel->parent_count = 0;
init_data->num_parents = 0;
kfree(init_data->parent_names);
init_data->parent_names = NULL;
}
static void peri_clk_teardown(struct peri_clk_data *data,
struct clk_init_data *init_data)
{
clk_sel_teardown(&data->sel, init_data);
init_data->ops = NULL;
}
/*
* Caller is responsible for freeing the parent_names[] and
* parent_sel[] arrays in the peripheral clock's "data" structure
* that can be assigned if the clock has one or more parent clocks
* associated with it.
*/
static int peri_clk_setup(struct ccu_data *ccu, struct peri_clk_data *data,
struct clk_init_data *init_data)
{
init_data->ops = &kona_peri_clk_ops;
init_data->flags = CLK_IGNORE_UNUSED;
return clk_sel_setup(data->clocks, &data->sel, init_data);
}
static void bcm_clk_teardown(struct kona_clk *bcm_clk)
{
switch (bcm_clk->type) {
case bcm_clk_peri:
peri_clk_teardown(bcm_clk->data, &bcm_clk->init_data);
break;
default:
break;
}
bcm_clk->data = NULL;
bcm_clk->type = bcm_clk_none;
}
static void kona_clk_teardown(struct clk *clk)
{
struct clk_hw *hw;
struct kona_clk *bcm_clk;
if (!clk)
return;
hw = __clk_get_hw(clk);
if (!hw) {
pr_err("%s: clk %p has null hw pointer\n", __func__, clk);
return;
}
clk_unregister(clk);
bcm_clk = to_kona_clk(hw);
bcm_clk_teardown(bcm_clk);
}
struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name,
enum bcm_clk_type type, void *data)
{
struct kona_clk *bcm_clk;
struct clk_init_data *init_data;
struct clk *clk = NULL;
bcm_clk = kzalloc(sizeof(*bcm_clk), GFP_KERNEL);
if (!bcm_clk) {
pr_err("%s: failed to allocate bcm_clk for %s\n", __func__,
name);
return NULL;
}
bcm_clk->ccu = ccu;
bcm_clk->name = name;
init_data = &bcm_clk->init_data;
init_data->name = name;
switch (type) {
case bcm_clk_peri:
if (peri_clk_setup(ccu, data, init_data))
goto out_free;
break;
default:
data = NULL;
break;
}
bcm_clk->type = type;
bcm_clk->data = data;
/* Make sure everything makes sense before we set it up */
if (!kona_clk_valid(bcm_clk)) {
pr_err("%s: clock data invalid for %s\n", __func__, name);
goto out_teardown;
}
bcm_clk->hw.init = init_data;
clk = clk_register(NULL, &bcm_clk->hw);
if (IS_ERR(clk)) {
pr_err("%s: error registering clock %s (%ld)\n", __func__,
name, PTR_ERR(clk));
goto out_teardown;
}
BUG_ON(!clk);
return clk;
out_teardown:
bcm_clk_teardown(bcm_clk);
out_free:
kfree(bcm_clk);
return NULL;
}
static void ccu_clks_teardown(struct ccu_data *ccu)
{
u32 i;
for (i = 0; i < ccu->data.clk_num; i++)
kona_clk_teardown(ccu->data.clks[i]);
kfree(ccu->data.clks);
}
static void kona_ccu_teardown(struct ccu_data *ccu)
{
if (!ccu)
return;
if (!ccu->base)
goto done;
of_clk_del_provider(ccu->node); /* safe if never added */
ccu_clks_teardown(ccu);
list_del(&ccu->links);
of_node_put(ccu->node);
iounmap(ccu->base);
done:
kfree(ccu->name);
kfree(ccu);
}
/*
* Set up a CCU. Call the provided ccu_clks_setup callback to
* initialize the array of clocks provided by the CCU.
*/
void __init kona_dt_ccu_setup(struct device_node *node,
int (*ccu_clks_setup)(struct ccu_data *))
{
struct ccu_data *ccu;
struct resource res = { 0 };
resource_size_t range;
int ret;
ccu = kzalloc(sizeof(*ccu), GFP_KERNEL);
if (ccu)
ccu->name = kstrdup(node->name, GFP_KERNEL);
if (!ccu || !ccu->name) {
pr_err("%s: unable to allocate CCU struct for %s\n",
__func__, node->name);
kfree(ccu);
return;
}
ret = of_address_to_resource(node, 0, &res);
if (ret) {
pr_err("%s: no valid CCU registers found for %s\n", __func__,
node->name);
goto out_err;
}
range = resource_size(&res);
if (range > (resource_size_t)U32_MAX) {
pr_err("%s: address range too large for %s\n", __func__,
node->name);
goto out_err;
}
ccu->range = (u32)range;
ccu->base = ioremap(res.start, ccu->range);
if (!ccu->base) {
pr_err("%s: unable to map CCU registers for %s\n", __func__,
node->name);
goto out_err;
}
spin_lock_init(&ccu->lock);
INIT_LIST_HEAD(&ccu->links);
ccu->node = of_node_get(node);
list_add_tail(&ccu->links, &ccu_list);
/* Set up clocks array (in ccu->data) */
if (ccu_clks_setup(ccu))
goto out_err;
ret = of_clk_add_provider(node, of_clk_src_onecell_get, &ccu->data);
if (ret) {
pr_err("%s: error adding ccu %s as provider (%d)\n", __func__,
node->name, ret);
goto out_err;
}
if (!kona_ccu_init(ccu))
pr_err("Broadcom %s initialization had errors\n", node->name);
return;
out_err:
kona_ccu_teardown(ccu);
pr_err("Broadcom %s setup aborted\n", node->name);
}

1033
drivers/clk/bcm/clk-kona.c Normal file
View File

File diff suppressed because it is too large Load Diff

410
drivers/clk/bcm/clk-kona.h Normal file
View File

@ -0,0 +1,410 @@
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CLK_KONA_H
#define _CLK_KONA_H
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/of.h>
#include <linux/clk-provider.h>
#define BILLION 1000000000
/* The common clock framework uses u8 to represent a parent index */
#define PARENT_COUNT_MAX ((u32)U8_MAX)
#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
#define BAD_CLK_NAME ((const char *)-1)
#define BAD_SCALED_DIV_VALUE U64_MAX
/*
* Utility macros for object flag management. If possible, flags
* should be defined such that 0 is the desired default value.
*/
#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
/* Clock field state tests */
#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
#define divider_has_fraction(div) (!divider_is_fixed(div) && \
(div)->frac_width > 0)
#define selector_exists(sel) ((sel)->width != 0)
#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
/* Clock type, used to tell common block what it's part of */
enum bcm_clk_type {
bcm_clk_none, /* undefined clock type */
bcm_clk_bus,
bcm_clk_core,
bcm_clk_peri
};
/*
* Each CCU defines a mapped area of memory containing registers
* used to manage clocks implemented by the CCU. Access to memory
* within the CCU's space is serialized by a spinlock. Before any
* (other) address can be written, a special access "password" value
* must be written to its WR_ACCESS register (located at the base
* address of the range). We keep track of the name of each CCU as
* it is set up, and maintain them in a list.
*/
struct ccu_data {
void __iomem *base; /* base of mapped address space */
spinlock_t lock; /* serialization lock */
bool write_enabled; /* write access is currently enabled */
struct list_head links; /* for ccu_list */
struct device_node *node;
struct clk_onecell_data data;
const char *name;
u32 range; /* byte range of address space */
};
/*
* Gating control and status is managed by a 32-bit gate register.
*
* There are several types of gating available:
* - (no gate)
* A clock with no gate is assumed to be always enabled.
* - hardware-only gating (auto-gating)
* Enabling or disabling clocks with this type of gate is
* managed automatically by the hardware. Such clocks can be
* considered by the software to be enabled. The current status
* of auto-gated clocks can be read from the gate status bit.
* - software-only gating
* Auto-gating is not available for this type of clock.
* Instead, software manages whether it's enabled by setting or
* clearing the enable bit. The current gate status of a gate
* under software control can be read from the gate status bit.
* To ensure a change to the gating status is complete, the
* status bit can be polled to verify that the gate has entered
* the desired state.
* - selectable hardware or software gating
* Gating for this type of clock can be configured to be either
* under software or hardware control. Which type is in use is
* determined by the hw_sw_sel bit of the gate register.
*/
struct bcm_clk_gate {
u32 offset; /* gate register offset */
u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
u32 en_bit; /* 0: disable; 1: enable */
u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
};
/*
* Gate flags:
* HW means this gate can be auto-gated
* SW means the state of this gate can be software controlled
* NO_DISABLE means this gate is (only) enabled if under software control
* SW_MANAGED means the status of this gate is under software control
* ENABLED means this software-managed gate is *supposed* to be enabled
*/
#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
/*
* Gate initialization macros.
*
* Any gate initially under software control will be enabled.
*/
/* A hardware/software gate initially under software control */
#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
FLAG(GATE, EXISTS), \
}
/* A hardware/software gate initially under hardware control */
#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, EXISTS), \
}
/* A hardware-or-enabled gate (enabled if not under hardware control) */
#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
}
/* A software-only gate */
#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
}
/* A hardware-only gate */
#define HW_ONLY_GATE(_offset, _status_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
}
/*
* Each clock can have zero, one, or two dividers which change the
* output rate of the clock. Each divider can be either fixed or
* variable. If there are two dividers, they are the "pre-divider"
* and the "regular" or "downstream" divider. If there is only one,
* there is no pre-divider.
*
* A fixed divider is any non-zero (positive) value, and it
* indicates how the input rate is affected by the divider.
*
* The value of a variable divider is maintained in a sub-field of a
* 32-bit divider register. The position of the field in the
* register is defined by its offset and width. The value recorded
* in this field is always 1 less than the value it represents.
*
* In addition, a variable divider can indicate that some subset
* of its bits represent a "fractional" part of the divider. Such
* bits comprise the low-order portion of the divider field, and can
* be viewed as representing the portion of the divider that lies to
* the right of the decimal point. Most variable dividers have zero
* fractional bits. Variable dividers with non-zero fraction width
* still record a value 1 less than the value they represent; the
* added 1 does *not* affect the low-order bit in this case, it
* affects the bits above the fractional part only. (Often in this
* code a divider field value is distinguished from the value it
* represents by referring to the latter as a "divisor".)
*
* In order to avoid dealing with fractions, divider arithmetic is
* performed using "scaled" values. A scaled value is one that's
* been left-shifted by the fractional width of a divider. Dividing
* a scaled value by a scaled divisor produces the desired quotient
* without loss of precision and without any other special handling
* for fractions.
*
* The recorded value of a variable divider can be modified. To
* modify either divider (or both), a clock must be enabled (i.e.,
* using its gate). In addition, a trigger register (described
* below) must be used to commit the change, and polled to verify
* the change is complete.
*/
struct bcm_clk_div {
union {
struct { /* variable divider */
u32 offset; /* divider register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 frac_width; /* field fraction width */
u64 scaled_div; /* scaled divider value */
};
u32 fixed; /* non-zero fixed divider value */
};
u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
};
/*
* Divider flags:
* EXISTS means this divider exists
* FIXED means it is a fixed-rate divider
*/
#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
/* Divider initialization macros */
/* A fixed (non-zero) divider */
#define FIXED_DIVIDER(_value) \
{ \
.fixed = (_value), \
.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
}
/* A divider with an integral divisor */
#define DIVIDER(_offset, _shift, _width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/* A divider whose divisor has an integer and fractional part */
#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.frac_width = (_frac_width), \
.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/*
* Clocks may have multiple "parent" clocks. If there is more than
* one, a selector must be specified to define which of the parent
* clocks is currently in use. The selected clock is indicated in a
* sub-field of a 32-bit selector register. The range of
* representable selector values typically exceeds the number of
* available parent clocks. Occasionally the reset value of a
* selector field is explicitly set to a (specific) value that does
* not correspond to a defined input clock.
*
* We register all known parent clocks with the common clock code
* using a packed array (i.e., no empty slots) of (parent) clock
* names, and refer to them later using indexes into that array.
* We maintain an array of selector values indexed by common clock
* index values in order to map between these common clock indexes
* and the selector values used by the hardware.
*
* Like dividers, a selector can be modified, but to do so a clock
* must be enabled, and a trigger must be used to commit the change.
*/
struct bcm_clk_sel {
u32 offset; /* selector register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 parent_count; /* number of entries in parent_sel[] */
u32 *parent_sel; /* array of parent selector values */
u8 clk_index; /* current selected index in parent_sel[] */
};
/* Selector initialization macro */
#define SELECTOR(_offset, _shift, _width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.clk_index = BAD_CLK_INDEX, \
}
/*
* Making changes to a variable divider or a selector for a clock
* requires the use of a trigger. A trigger is defined by a single
* bit within a register. To signal a change, a 1 is written into
* that bit. To determine when the change has been completed, that
* trigger bit is polled; the read value will be 1 while the change
* is in progress, and 0 when it is complete.
*
* Occasionally a clock will have more than one trigger. In this
* case, the "pre-trigger" will be used when changing a clock's
* selector and/or its pre-divider.
*/
struct bcm_clk_trig {
u32 offset; /* trigger register offset */
u32 bit; /* trigger bit */
u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
};
/*
* Trigger flags:
* EXISTS means this trigger exists
*/
#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
/* Trigger initialization macro */
#define TRIGGER(_offset, _bit) \
{ \
.offset = (_offset), \
.bit = (_bit), \
.flags = FLAG(TRIG, EXISTS), \
}
struct peri_clk_data {
struct bcm_clk_gate gate;
struct bcm_clk_trig pre_trig;
struct bcm_clk_div pre_div;
struct bcm_clk_trig trig;
struct bcm_clk_div div;
struct bcm_clk_sel sel;
const char *clocks[]; /* must be last; use CLOCKS() to declare */
};
#define CLOCKS(...) { __VA_ARGS__, NULL, }
#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
struct kona_clk {
struct clk_hw hw;
struct clk_init_data init_data;
const char *name; /* name of this clock */
struct ccu_data *ccu; /* ccu this clock is associated with */
enum bcm_clk_type type;
union {
void *data;
struct peri_clk_data *peri;
};
};
#define to_kona_clk(_hw) \
container_of(_hw, struct kona_clk, hw)
/* Exported globals */
extern struct clk_ops kona_peri_clk_ops;
/* Help functions */
#define PERI_CLK_SETUP(clks, ccu, id, name) \
clks[id] = kona_clk_setup(ccu, #name, bcm_clk_peri, &name ## _data)
/* Externally visible functions */
extern u64 do_div_round_closest(u64 dividend, unsigned long divisor);
extern u64 scaled_div_max(struct bcm_clk_div *div);
extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value,
u32 billionths);
extern struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name,
enum bcm_clk_type type, void *data);
extern void __init kona_dt_ccu_setup(struct device_node *node,
int (*ccu_clks_setup)(struct ccu_data *));
extern bool __init kona_ccu_init(struct ccu_data *ccu);
#endif /* _CLK_KONA_H */

65
include/dt-bindings/clock/bcm281xx.h Normal file
View File

@ -0,0 +1,65 @@
/*
* Copyright (C) 2013 Broadcom Corporation
* Copyright 2013 Linaro Limited
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CLOCK_BCM281XX_H
#define _CLOCK_BCM281XX_H
/*
* This file defines the values used to specify clocks provided by
* the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
*/
/* root CCU clock ids */
#define BCM281XX_ROOT_CCU_FRAC_1M 0
#define BCM281XX_ROOT_CCU_CLOCK_COUNT 1
/* aon CCU clock ids */
#define BCM281XX_AON_CCU_HUB_TIMER 0
#define BCM281XX_AON_CCU_PMU_BSC 1
#define BCM281XX_AON_CCU_PMU_BSC_VAR 2
#define BCM281XX_AON_CCU_CLOCK_COUNT 3
/* hub CCU clock ids */
#define BCM281XX_HUB_CCU_TMON_1M 0
#define BCM281XX_HUB_CCU_CLOCK_COUNT 1
/* master CCU clock ids */
#define BCM281XX_MASTER_CCU_SDIO1 0
#define BCM281XX_MASTER_CCU_SDIO2 1
#define BCM281XX_MASTER_CCU_SDIO3 2
#define BCM281XX_MASTER_CCU_SDIO4 3
#define BCM281XX_MASTER_CCU_USB_IC 4
#define BCM281XX_MASTER_CCU_HSIC2_48M 5
#define BCM281XX_MASTER_CCU_HSIC2_12M 6
#define BCM281XX_MASTER_CCU_CLOCK_COUNT 7
/* slave CCU clock ids */
#define BCM281XX_SLAVE_CCU_UARTB 0
#define BCM281XX_SLAVE_CCU_UARTB2 1
#define BCM281XX_SLAVE_CCU_UARTB3 2
#define BCM281XX_SLAVE_CCU_UARTB4 3
#define BCM281XX_SLAVE_CCU_SSP0 4
#define BCM281XX_SLAVE_CCU_SSP2 5
#define BCM281XX_SLAVE_CCU_BSC1 6
#define BCM281XX_SLAVE_CCU_BSC2 7
#define BCM281XX_SLAVE_CCU_BSC3 8
#define BCM281XX_SLAVE_CCU_PWM 9
#define BCM281XX_SLAVE_CCU_CLOCK_COUNT 10
#endif /* _CLOCK_BCM281XX_H */