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ACPICA: Implement IVRS IVHD type 11h parsing

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ACPICA commit 6ddc19419896e4149ced1b5f35f0dc12516c0399

The AMD IVRS table parsing supported only IVHD type 10h structures.
Parsing an IVHD type 11h caused the iasl to report unknown subtable type.
Add necessary structure definition for IVHD type 11h and apply correct
parsing method based on subtable type.

Link: https://github.com/acpica/acpica/commit/6ddc1941
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Erik Kaneda <erik.kaneda@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Michał Żygowski 2020-03-27 15:21:02 -07:00 committed by Rafael J. Wysocki
parent 1c040f3a6a
commit 1f6239ca16
1 changed files with 16 additions and 2 deletions
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18
include/acpi/actbl2.h
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@ -274,7 +274,8 @@ struct acpi_ivrs_header {
/* Values for subtable Type above */ /* Values for subtable Type above */
enum acpi_ivrs_type { enum acpi_ivrs_type {
ACPI_IVRS_TYPE_HARDWARE = 0x10, ACPI_IVRS_TYPE_HARDWARE1 = 0x10,
ACPI_IVRS_TYPE_HARDWARE2 = 0x11,
ACPI_IVRS_TYPE_MEMORY1 = 0x20, ACPI_IVRS_TYPE_MEMORY1 = 0x20,
ACPI_IVRS_TYPE_MEMORY2 = 0x21, ACPI_IVRS_TYPE_MEMORY2 = 0x21,
ACPI_IVRS_TYPE_MEMORY3 = 0x22 ACPI_IVRS_TYPE_MEMORY3 = 0x22
@ -301,7 +302,7 @@ enum acpi_ivrs_type {
/* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */ /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */
struct acpi_ivrs_hardware { struct acpi_ivrs_hardware_10 {
struct acpi_ivrs_header header; struct acpi_ivrs_header header;
u16 capability_offset; /* Offset for IOMMU control fields */ u16 capability_offset; /* Offset for IOMMU control fields */
u64 base_address; /* IOMMU control registers */ u64 base_address; /* IOMMU control registers */
@ -310,6 +311,19 @@ struct acpi_ivrs_hardware {
u32 reserved; u32 reserved;
}; };
/* 0x11: I/O Virtualization Hardware Definition Block (IVHD) */
struct acpi_ivrs_hardware_11 {
struct acpi_ivrs_header header;
u16 capability_offset; /* Offset for IOMMU control fields */
u64 base_address; /* IOMMU control registers */
u16 pci_segment_group;
u16 info; /* MSI number and unit ID */
u32 attributes;
u64 efr_register_image;
u64 reserved;
};
/* Masks for Info field above */ /* Masks for Info field above */
#define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ #define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */