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arm64: dts: Add ipq6018 SoC and CP01 board support
Add initial device tree support for the Qualcomm IPQ6018 SoC and CP01 evaluation board. Co-developed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Co-developed-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Link: https://lore.kernel.org/r/1579439601-14810-5-git-send-email-sricharan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sricharan R
Bjorn Andersson
parent
2f0c17faeb
commit
1e8277854b
@ -2,6 +2,7 @@
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dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
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30
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
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30
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
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@ -0,0 +1,30 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ6018 CP01 board device tree source
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*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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/dts-v1/;
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#include "ipq6018.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1";
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compatible = "qcom,ipq6018-cp01", "qcom,ipq6018";
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aliases {
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serial0 = &blsp1_uart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs-append = " swiotlb=1";
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};
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};
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&blsp1_uart3 {
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pinctrl-0 = <&serial_3_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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217
arch/arm64/boot/dts/qcom/ipq6018.dtsi
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217
arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@ -0,0 +1,217 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* IPQ6018 SoC device tree source
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*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&intc>;
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clocks {
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <0x2>;
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};
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};
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pmuv8: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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tz: tz@48500000 {
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reg = <0x0 0x48500000 0x0 0x00200000>;
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no-map;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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dma-ranges;
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compatible = "simple-bus";
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq6018-pinctrl";
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reg = <0x01000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 80>;
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interrupt-controller;
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#interrupt-cells = <2>;
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serial_3_pins: serial3-pinmux {
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pins = "gpio44", "gpio45";
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function = "blsp2_uart";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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gcc: gcc@1800000 {
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compatible = "qcom,gcc-ipq6018";
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reg = <0x01800000 0x80000>;
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clocks = <&xo>, <&sleep_clk>;
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clock-names = "xo", "sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x0b000000 0x1000>, /*GICD*/
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<0x0b002000 0x1000>, /*GICC*/
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<0x0b001000 0x1000>, /*GICH*/
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<0x0b004000 0x1000>; /*GICV*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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timer@b120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x0b120000 0x1000>;
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clock-frequency = <19200000>;
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frame@b120000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b121000 0x1000>,
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<0x0b122000 0x1000>;
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};
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frame@b123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xb123000 0x1000>;
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status = "disabled";
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};
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frame@b124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b124000 0x1000>;
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status = "disabled";
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};
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frame@b125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b125000 0x1000>;
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status = "disabled";
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};
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frame@b126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b126000 0x1000>;
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status = "disabled";
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};
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frame@b127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b127000 0x1000>;
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status = "disabled";
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};
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frame@b128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0b128000 0x1000>;
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status = "disabled";
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};
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};
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};
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};
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