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riscv: atomic: Optimize dec_if_positive functions
Current implementation wastes another register to pass the argument, but we only need addi to calculate the result. Optimize the code with minimize the usage of registers. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Link: https://lore.kernel.org/r/20220505035526.2974382-3-guoren@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -310,47 +310,47 @@ ATOMIC_OPS()
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#undef ATOMIC_OPS
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#undef ATOMIC_OP
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static __always_inline int arch_atomic_sub_if_positive(atomic_t *v, int offset)
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static __always_inline int arch_atomic_dec_if_positive(atomic_t *v)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0: lr.w %[p], %[c]\n"
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" sub %[rc], %[p], %[o]\n"
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" addi %[rc], %[p], -1\n"
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" bltz %[rc], 1f\n"
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" sc.w.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [o]"r" (offset)
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:
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: "memory");
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return prev - offset;
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return prev - 1;
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}
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#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(v, 1)
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#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive
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#ifndef CONFIG_GENERIC_ATOMIC64
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static __always_inline s64 arch_atomic64_sub_if_positive(atomic64_t *v, s64 offset)
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static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
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{
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s64 prev;
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long rc;
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__asm__ __volatile__ (
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"0: lr.d %[p], %[c]\n"
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" sub %[rc], %[p], %[o]\n"
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" addi %[rc], %[p], -1\n"
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" bltz %[rc], 1f\n"
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" sc.d.rl %[rc], %[rc], %[c]\n"
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" bnez %[rc], 0b\n"
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" fence rw, rw\n"
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"1:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter)
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: [o]"r" (offset)
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:
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: "memory");
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return prev - offset;
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return prev - 1;
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}
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#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(v, 1)
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#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
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#endif
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#endif /* _ASM_RISCV_ATOMIC_H */
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