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drm/i915: start writing infoframes at address 0 on gen 4
Make sure we're doing the right thing, just like we do on gen5+. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -132,7 +132,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
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else
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return;
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val &= ~VIDEO_DIP_SELECT_MASK;
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= intel_infoframe_index(frame);
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val |= VIDEO_DIP_ENABLE;
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